3D Semiconductor Memory Integration Density via Vertical Stacking
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in increasing integration density due to the cost of advanced process equipment required for finer pattern formation, making three-dimensional semiconductor memory devices necessary for improved reliability and higher integration.
Innovation Solution
A semiconductor memory device with a cell array structure featuring horizontal and vertical conductive patterns, a power capacitor in a planarization insulating layer, and bonding pads connected to both memory cells and peripheral circuits, allowing for increased integration density without expanding device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density cannot be increased sufficiently
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional stacked structures by vertically stacking multiple memory cell layers. Each layer includes bit lines, word lines, and memory elements arranged in three-dimensional space, enabling increased integration density without being constrained by planar area limitations.
2Quantity of substance
If three-dimensional stacked structures are implemented, then integration density increases, but manufacturing precision requirements increase
Solution Approach 1:
The three-dimensional memory structure is divided into multiple discrete layers, each containing complete sets of bit lines, word lines, and memory elements. This segmentation into repeatable unit layers allows for modular manufacturing processes, where each layer can be formed with standardized precision requirements, reducing the overall manufacturing complexity compared to forming a monolithic three-dimensional structure.
Data Source
AI summary
A semiconductor memory device may include a cell array structure including first bonding pads, which are electrically connected to memory cells, and a peripheral circuit structure including second bonding pads, which are electrically connected to peripheral circuits and are bonded to the first bonding pads. The cell array structure may include a stack including horizontal conductive patterns stacked in a vertical direction, a vertical structure including vertical conductive patterns , which are provided to cross the stack in the vertical direction, and a power capacitor provided in a planarization insulating layer covering a portion of the stack.