3D Semiconductor Memory Device Vertical Channel Integration
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Solution Overview
Problem
The integration density of two-dimensional semiconductor memory devices is limited by the cost of equipment used for forming fine patterns, leading to the development of three-dimensional devices, but these also face challenges in manufacturing costs and efficiency.
Innovation Solution
A semiconductor memory device design featuring a substrate with a cell array and peripheral circuit region, including a ground selection line, word line, insulating layer, and vertical channel portion, where the insulating layer extends from the cell array to the peripheral circuit region to cover the top surface of the peripheral circuit gate pattern, enhancing integration density and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor memory devices are developed to increase integration density, then integration density is improved, but manufacturing cost increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertical channel structures. The vertical channel portions extend perpendicular to the substrate surface, allowing multiple memory cells to be stacked vertically. This dimensional change enables higher integration density without proportionally increasing manufacturing complexity, as the vertical stacking can be achieved through sequential deposition and etching processes rather than requiring more expensive fine-patterning equipment.
Solution Approach 2:
The memory device is segmented into multiple functional layers including ground selection lines, word lines, insulating layers, and vertical channel portions. Each layer is formed through separate deposition and patterning steps, allowing for modular manufacturing. The ground selection lines and word lines are divided into multiple stacks at different heights, enabling independent formation and simplifying the overall fabrication process while achieving high integration density.
2Quantity of substance
If fine pattern forming techniques are used to increase integration density in 2D devices, then integration density is improved, but manufacturing cost increases
Solution Approach 1:
Instead of increasing integration density through finer lateral patterning in the 2D plane, the patent utilizes the vertical dimension by forming channel portions that extend perpendicular to the substrate. This approach achieves higher density through vertical stacking rather than lateral miniaturization, avoiding the need for expensive fine-patterning equipment while maintaining manufacturability through standard deposition and etching processes.
Solution Approach 2:
The ground selection lines and insulating layers are formed in advance before the vertical channel portions are created. This preliminary formation of the structural framework allows subsequent channel formation to proceed through simpler processes, reducing overall manufacturing complexity while achieving high integration density through the pre-established vertical architecture.
Data Source
AI summary
A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.