3D Semiconductor Memory Device Vertical Channel Pillars
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Solution Overview
Problem
The demand for high integration in semiconductor memory devices is limited by the constraints of photolithography processes, making it challenging to further reduce the minimum line width of fine patterns, which hinders the increase in memory cell density.
Innovation Solution
A semiconductor memory device with a three-dimensional structure is developed, featuring wordline and bitline transistors with channel pillars penetrating the gates, local and global wordlines and bitlines, and variable resistors at intersections, allowing for high integration and efficient memory cell arrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum line width of fine patterns is shortened to increase memory cell density, then integration level is improved, but photolithography process limits are reached making further shortening difficult
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertical channel transistors. The channel extends vertically through the substrate thickness rather than laterally, allowing memory cell density to increase by utilizing the third dimension (depth) instead of further reducing the minimum line width in the planar direction. This dimensional change bypasses photolithography process limits.
2Quantity of substance
If three-dimensional vertical channel transistors are used to increase integration, then memory cell density is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple stacked memory cell layers, with each layer containing complete wordline and bitline transistor sets. This segmentation allows the complex three-dimensional structure to be organized into manageable, repeating units, simplifying the overall device architecture while maintaining high density.
Solution Approach 2:
The vertical channel transistors serve multiple functions: they act as both wordline transistors and bitline transistors depending on which gate electrode controls them. This multi-functionality reduces the total number of transistor components needed, thereby reducing device complexity while maintaining high memory cell density.
Data Source
AI summary
Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.