Semiconductor Memory Device with Vertical FinFET Structure
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing memory cell area and parasitic capacitance, particularly with planar transistors and recessed channel array transistors, which limit further miniaturization and increase capacitance, making it difficult to achieve smaller feature sizes and higher integration densities.
Innovation Solution
The design incorporates a bit line positioned below a semiconductor region with contacts at the groove bottom and a capacitor contact at the top between grooves, allowing for a reduced memory cell area of 4F2, reduced parasitic capacitance, and efficient integration by using a folded bit line structure with word lines on the side surfaces of grooves, enabling a more integrated and reliable semiconductor memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If planar transistors or RCAT are used, then the device structure is simple and easy to manufacture, but the memory cell area cannot be reduced below 6F2-8F2
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional FinFET structures with vertical channels. The FinFET configuration utilizes vertical fins extending from the substrate, allowing the channel to be controlled from three sides by the gate, thereby achieving higher integration density (4F2 area) while maintaining manufacturability through established semiconductor processing techniques.
Solution Approach 2:
The patent implements nested structures where capacitors are positioned beneath the bit lines, and multiple functional layers are stacked vertically. This nesting approach allows compact arrangement of memory cell components, reducing the overall footprint while maintaining electrical functionality and signal integrity.
2Object-generated harmful factors
If conventional transistor structures are used, then manufacturing is easier, but parasitic capacitance of bit lines increases
Solution Approach 1:
The patent extracts the capacitor from its conventional position adjacent to the bit line and relocates it beneath the bit line structure. This separation removes the primary source of parasitic capacitance between the bit line and capacitor, significantly reducing unwanted electrical coupling while preserving the memory cell's read/write functionality.
Solution Approach 2:
The patent moves capacitor placement from a lateral arrangement (side-by-side with bit line) to a vertical stacking arrangement (beneath the bit line). This dimensional change reduces the overlapping area between conductive elements, thereby minimizing parasitic capacitance while maintaining compact cell area.
3Productivity
If feature size is reduced to increase integration density, then more memory cells fit in the same area, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the transistor channel into vertical fins with controlled dimensions, where the fin width and height can be independently optimized. This segmentation allows the channel length to be effectively increased through fin height while maintaining small footprint, thereby achieving high integration density with relaxed line width control requirements compared to planar structures.
Solution Approach 2:
The patent changes the geometric parameters of the transistor from two-dimensional planar dimensions to three-dimensional FinFET parameters (fin width, fin height, fin spacing). This parameter transformation enables scaling to smaller feature sizes while maintaining manufacturability, as the vertical fin structure provides better channel control and reduced short-channel effects at small dimensions.
Data Source
AI summary
A highly integrated DRAM is provided. A bit line is formed over a first insulator, a second insulator is formed over the bit line, third insulators which are in a stripe shape and the like are formed over the second insulator, and a semiconductor region and a gate insulator are formed to cover one of the third insulators. The bit line is connected to the semiconductor region through first contact plugs. Then, a conductive film is formed and subjected to anisotropic etching to form word lines at side surfaces of the third insulators, and a second contact plug is formed to be connected to a capacitor at a top of the one of the third insulators. By synchronizing the word lines, electric charge is accumulated or released through the capacitor. With such a structure, the area of a memory cell can be 4F2.