Semiconductor Memory Layout Using Vertical Conductive Layers
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Solution Overview
Problem
Conventional dual port SRAM structures require a large footprint to avoid resistive and capacitive coupling issues due to the spacing needed between bit lines and voltage supply lines, limiting memory density and speed.
Innovation Solution
The proposed layout achieves symmetric resistance and capacitive loading across word lines by optimizing the arrangement of conductive layers and interconnects, reducing the footprint of memory bit cells and shortening interconnects, which allows for increased density and faster operating times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple bit lines and voltage supply lines are placed in a single conductive layer, then the structure is simpler, but the footprint increases due to required spacing to avoid RC coupling issues
Solution Approach 1:
The patent distributes bit lines and voltage supply lines across multiple conductive layers (first conductive layer for bit lines, second conductive layer for voltage supply lines) instead of placing them all in a single layer. This vertical separation in the z-dimension eliminates the need for lateral spacing, reducing the memory cell footprint while maintaining electrical isolation to prevent RC coupling issues.
2Reliability
If larger spacing is provided between bit lines and voltage supply lines, then RC coupling issues are reduced, but the memory cell footprint increases
Solution Approach 1:
The invention moves the voltage supply lines from the same conductive layer as bit lines to a separate second conductive layer. This vertical separation provides electrical isolation and reduces RC coupling without requiring increased lateral spacing, thus maintaining small memory cell footprint while improving signal integrity.
Solution Approach 2:
The patent introduces a dielectric layer between the first conductive layer (bit lines) and second conductive layer (voltage supply lines) as an intermediary medium. This dielectric layer provides electrical isolation, reducing capacitive coupling between bit lines and voltage supply lines while allowing compact lateral arrangement.
3Ease of manufacture
If conventional layouts are used, then manufacturing is simpler, but operating speed is limited due to larger cell size and longer interconnects
Solution Approach 1:
The patent employs multiple conductive layers to vertically separate bit lines and voltage supply lines, enabling compact lateral arrangement of memory cell components. This reduces cell size and interconnect lengths, thereby increasing operating speed while remaining compatible with standard semiconductor manufacturing processes for multi-layer structures.
Data Source
AI summary
A semiconductor memory includes a first conductive layer including a first pair of bit lines coupled to a first bit cell and a second conductive layer including a second pair of bit lines coupled to the first bit cell. The first and second conductive layers are vertically separated from each other.