3D Semiconductor Memory Device Vertical Stacking Integration
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Solution Overview
Problem
2D semiconductor memory devices face integration limits and interference issues as memory cell sizes shrink, making multi-level cell operations difficult, whereas 3D semiconductor memory devices can efficiently utilize semiconductor substrate area with a stacked structure, allowing for improved integration.
Innovation Solution
A 3D semiconductor memory device is designed with vertically stacked cell strings, bit lines, and source lines connected to vertical channel layers, and a peripheral circuit with switching devices, allowing for partial overlap between the memory block and peripheral circuit regions to enhance integration and reduce size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is shrunk in 2D semiconductor memory devices, then integration density can be improved, but interference and disturbance increase making multi-level cell operations difficult
Solution Approach 1:
The patent transitions from 2D planar arrangement to 3D vertical stacking of cell strings. Cell strings are arranged vertically on the semiconductor substrate with select lines, word lines, and channel structures stacked in the vertical direction, enabling improved integration density while maintaining adequate spacing between memory cells to reduce interference and disturbance.
2Area of stationary object
If 3D stacked structure is implemented, then substrate area utilization is improved, but manufacturing complexity increases
Solution Approach 1:
The 3D stacked structure is divided into discrete horizontal layers including bottom electrode layer, first insulating layer, tunnel insulating layer, charge storage layer, blocking insulating layer, top electrode layer, and upper insulating layer. Each layer is formed through separate manufacturing steps, allowing systematic fabrication and control of the complex 3D structure.
Solution Approach 2:
The patent implements a nested structure where the vertical channel layer is surrounded by tunnel insulating layer, which is surrounded by charge storage layer, which is surrounded by blocking insulating layer. This nested arrangement of concentric cylindrical layers simplifies the manufacturing process by using sequential deposition techniques.
3Volume of moving object
If peripheral circuit and memory block regions are overlapped, then device size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes vertical stacking to overlap the peripheral circuit region with the memory block region in the vertical direction. Switching devices are formed in the peripheral circuit region below the memory block, allowing horizontal space reduction while maintaining functional separation through vertical layering.
Data Source
AI summary
Provided are a semiconductor device. The semiconductor device includes a memory block including a drain select line, word lines, and a source select line, which are spaced apart from one another and stacked in a direction perpendicular to a semiconductor substrate; and a peripheral circuit including a switching device connected to a bit line, which is disposed under a vertical channel layer vertically passing through the drain select line, the word lines, and the source select line.