Semiconductor Memory Integration with Vertical Cell Positioning
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Solution Overview
Problem
Next-generation semiconductor memory devices require a design that integrates different operating characteristics of memory cells, such as DRAM and variable resistance memory cells, on a single substrate to enhance performance and efficiency while maintaining low power consumption.
Innovation Solution
A semiconductor device is designed with a first memory section comprising DRAM cell arrays and a second memory section comprising variable resistance memory cell arrays, both with distinct peripheral circuit sections and wiring configurations, allowing for side-by-side integration on a substrate with the second memory section's cells being positioned higher than the capacitors, enabling efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If different memory cell types (DRAM and variable resistance) are integrated on a single substrate, then device performance and efficiency are enhanced, but device complexity increases
Solution Approach 1:
The substrate is divided into distinct first and second memory sections, each dedicated to a specific memory cell type (DRAM and variable resistance respectively). This segmentation allows each memory type to operate with its optimized circuit design while maintaining integration on a single substrate, thus enhancing overall device performance without excessive complexity increase
Solution Approach 2:
The semiconductor device is designed to perform multiple memory functions simultaneously by integrating different memory cell types on one substrate. The device can operate as both volatile (DRAM) and nonvolatile (variable resistance) memory, providing multi-functionality that enhances productivity while managing complexity through unified substrate integration
2Productivity
If second memory cells are positioned higher than capacitors, then integration efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes vertical positioning (height dimension) to resolve layout conflicts between different memory cell components. By positioning the second memory cells at a higher elevation than the capacitors in the first memory section, the design achieves better integration efficiency in the vertical dimension while managing the precision requirements through structured layering
Data Source
AI summary
A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.