3D Semiconductor Memory With Vertical Sidewall Selection Components
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Solution Overview
Problem
As semiconductor devices are scaled down, the integration density and reliability of components become challenging due to narrow manufacturing margins and difficulty in optimizing characteristics of driving circuits and memory cells.
Innovation Solution
The semiconductor device design includes lower and upper interconnections with selection components at crossing points, and memory components between them, where the selection components have specific sidewall widths and are formed using a method involving trench formation, sacrificial lines, and epitaxial growth to achieve improved integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are scaled down to increase integration density, then integration density is improved, but manufacturing precision and reliability deteriorate due to narrow manufacturing margins
Solution Approach 1:
The patent transitions from planar 2D device layout to 3D vertical structures by forming trenches in the semiconductor substrate and growing semiconductor patterns vertically within these trenches. This dimensional change allows higher integration density without proportionally reducing lateral feature sizes, thereby maintaining manufacturing precision margins.
Solution Approach 2:
The patent changes the physical and chemical parameters of the semiconductor structure by forming specific doping profiles (first and second dopant regions with different conductivity types) and controlling the crystalline orientation of vertically grown semiconductor patterns. These parameter changes enable optimized device characteristics while maintaining manufacturability.
2Quantity of substance
If minimum widths of semiconductor devices are reduced to increase integration, then integration density is improved, but reliability deteriorates due to small process margins
Solution Approach 1:
By growing semiconductor patterns vertically in trenches rather than expanding laterally, the patent achieves higher integration density while maintaining larger lateral dimensions. This vertical growth approach preserves process margins and reliability by avoiding excessive miniaturization in the lateral direction.
Solution Approach 2:
The patent performs preliminary actions by forming mold patterns and sacrificial structures before growing the semiconductor patterns. These preliminary structures guide the vertical growth process and ensure precise formation of the semiconductor device structures, thereby maintaining reliability.
3Quantity of substance
If device size is reduced to increase integration, then integration density is improved, but difficulty in optimizing component characteristics increases
Solution Approach 1:
The patent applies local quality by creating distinct regions within the semiconductor device structure, including first dopant regions with one conductivity type and second dopant regions with opposite conductivity type. Each region is optimized for its specific function, allowing independent optimization of driving circuits and memory cells while achieving high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of semiconductor devices with enhanced integration density and reliability by forming semiconductor patterns with precise sidewall dimensions and structures, allowing for efficient current control and data storage.
Implementation Method 1
forming semiconductor patterns grown from the semiconductor substrate exposed by the openings
Data Source
AI summary
Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.