3D Semiconductor Memory Device Vertical Stacking Integration
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in increasing integration density due to the high cost of fine pattern forming technology, necessitating the development of three-dimensional semiconductor memory devices with vertically stacked memory cells.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a substrate having a cell region and a contact region, featuring vertically stacked semiconductor patterns, bit lines extending horizontally, and a word line adjacent to the semiconductor patterns, along with a peripheral transistor between the bit lines of different stacks, allowing for increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional or planar semiconductor devices are used, then the fabrication process is simpler, but the integration density is limited due to the area occupied by unit memory cells
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked in the vertical direction above each bit line, enabling integration density to scale with the third dimension rather than being constrained to the planar area, thus resolving the contradiction between integration density and fabrication complexity
2Manufacturing precision
If three-dimensional vertically stacked memory cells are implemented, then integration density increases, but the fabrication process becomes more complex and expensive
Solution Approach 1:
The patent merges the formation of memory cell stacks and peripheral circuit transistors into a single integrated structure. The peripheral transistor is formed between adjacent memory cell stacks, sharing common bit lines and utilizing the same vertical stacking architecture, which simplifies the fabrication process while maintaining high integration density
Solution Approach 2:
The bit lines serve multiple functions: they act as word lines for adjacent memory cell stacks and as source/drain regions for the peripheral transistor. This multi-functionality reduces the number of separate components and fabrication steps required, easing the manufacturing process while achieving high integration density
3Productivity
If more memory cells are integrated on the substrate, then performance improves, but the area occupied by unit memory cells limits further integration
Solution Approach 1:
By stacking memory cells vertically, the patent increases the number of memory cells per unit area without expanding the substrate footprint. Multiple memory cells share the same planar area through vertical stacking, enabling performance improvement while maintaining compact device area
Data Source
AI summary
A semiconductor memory device includes a substrate having a cell region and a contact region with a peripheral circuit region, first and second stacks on the cell region, and a first peripheral transistor on the peripheral circuit region. Each of the first and second stacks includes semiconductor patterns stacked, in a vertical direction, on the cell region, bit lines stacked in the vertical direction on the cell region and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending, in a horizontal direction with respect to the upper surface of the substrate, from the cell region to the contact region, and a word line disposed adjacent to the semiconductor patterns and extending in the vertical direction from the cell region of the substrate. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.