Semiconductor Memory Structure for Void-Free Conductive Filling
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Solution Overview
Problem
The shrinking size of semiconductor devices leads to increased capacitive coupling, leakage current, and short circuits, along with difficulties in filling processes that result in voids or seams, affecting the reliability and electrical performance of memory devices.
Innovation Solution
The solution involves improving the control accuracy of the etch-back process by enhancing the uniformity of the planarization process and combining it with the implantation process to adjust the aspect ratio of openings and trenches, thereby reducing the likelihood of voids or seams during the filling process, and using the implantation process to create a larger width at the top of openings and trenches for better filling capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of memory devices continues to shrink, then the integration density is improved, but capacitive coupling between adjacent elements increases and leakage current problems occur
Solution Approach 1:
The patent segments the conductive fill material into multiple layers (first conductive layer and second conductive layer) separated by an interlayer dielectric layer. This segmentation reduces capacitive coupling between adjacent conductive elements by introducing dielectric material between them, while maintaining high integration density through vertical stacking of conductive layers
Solution Approach 2:
The interlayer dielectric layer serves as an intermediary material between the first and second conductive layers. This dielectric layer acts as an electrical insulator that prevents leakage current between conductive layers while allowing the structure to maintain compact dimensions for high integration density
2Quantity of substance
If the size of memory devices continues to shrink, then the integration density is improved, but short circuit problems occur
Solution Approach 1:
The conductive structure is segmented into multiple isolated layers separated by dielectric material, preventing short circuits between adjacent conductive elements while maintaining high integration density through vertical arrangement
Solution Approach 2:
The interlayer dielectric layer acts as an intermediary insulating barrier between conductive layers, preventing electrical short circuits while enabling compact device design for high integration density
3Quantity of substance
If the filling process is performed in continuously shrinking structures, then the integration density is improved, but voids or seams are formed in the fill material
Solution Approach 1:
The filling process is segmented into multiple stages, with each conductive layer being filled separately. This allows each filling operation to work on a manageable scale with optimal aspect ratio, avoiding void formation while achieving high integration density through vertical stacking
Solution Approach 2:
The patent transitions from filling deep trenches in the vertical dimension to filling shallower layers in the horizontal dimension by stacking multiple conductive layers. This dimensional approach reduces the aspect ratio of each fill operation, improving filling quality and reducing voids while maintaining high integration density
4Ease of manufacture
If the aspect ratio of openings and trenches is adjusted, then the filling capability is improved, but the planarization process uniformity must be maintained
Solution Approach 1:
The structure is segmented into multiple conductive layers with intermediate dielectric layers, allowing each layer to have optimized dimensions for filling. The planarization process can then work on flattened surfaces between layers, maintaining uniformity while achieving good filling capability in each segment
Solution Approach 2:
Planarization processes are performed as preliminary steps before filling operations to create uniform, flat surfaces. This preliminary planarization ensures that subsequent filling processes can proceed with good uniformity and complete coverage, improving filling capability while maintaining manufacturing precision
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a pad layer, a first conductive layer, a second conductive layer, an interlayer dielectric layer, and a control gate. The pad layer is disposed on a substrate. The first conductive layer is disposed on the pad layer. The second conductive layer is disposed on the first conductive layer. The interlayer dielectric layer is disposed on the first conductive layer and the second conductive layer and is in contact with top surfaces of the first conductive layer and the second conductive layer. The control gate is disposed on the interlayer dielectric layer.