Semiconductor Memory Device Volatile Nonvolatile Switching
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high-speed operation and low power consumption, especially in volatile memory applications like SRAM, where data retention and efficient power management are critical.
Innovation Solution
The semiconductor device incorporates a data holding portion connected to a transistor with low off-state current, allowing for high-speed data writing and retention by switching between volatile and non-volatile memory states using a specific configuration of transistors and capacitors, optimizing power usage during save operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a volatile memory (SRAM) is used for high-speed operation, then operation speed is improved, but power consumption increases and data retention is lost when power is stopped
Solution Approach 1:
The patent applies dynamics by making the memory system adaptable between volatile and non-volatile states. The transistor switching mechanism dynamically changes the memory's characteristics: during active operation, the memory operates in volatile mode for high speed; during save operations, it transitions to non-volatile mode for low power consumption and data retention. This dynamic state change resolves the contradiction between speed and power consumption.
Solution Approach 2:
The patent changes the electrical parameters of the memory system by controlling transistor states. By adjusting the on/off state of transistors connecting to non-volatile memory elements, the system changes its effective capacitance and resistance characteristics, enabling it to switch between high-speed volatile operation and low-power non-volatile retention modes.
2Speed
If data is retained in volatile memory, then fast access is achieved, but data is lost when power is stopped
Solution Approach 1:
The patent implements preliminary action by performing save operations before power is stopped. The system proactively transfers data from volatile to non-volatile memory elements in advance, ensuring data is preserved before the power interruption occurs. This preliminary data protection mechanism resolves the contradiction between fast access and data retention.
Solution Approach 2:
The patent uses transistors as intermediary elements that control the connection between volatile and non-volatile memory portions. These intermediary transistors enable selective data transfer and isolation, allowing the system to maintain data in volatile memory for fast access while having the capability to transfer it to non-volatile memory for retention, thus resolving the contradiction.
3Reliability
If transistors are kept on for data retention, then data is preserved, but power consumption increases
Solution Approach 1:
The patent segments the memory into volatile and non-volatile portions with separate control mechanisms. By dividing the memory system and using different retention strategies for each segment, the system can keep only essential transistors on for data retention while transferring data to non-volatile elements, thereby reducing overall power consumption while maintaining data reliability.
Solution Approach 2:
The patent implements periodic save operations where data is transferred from volatile to non-volatile memory at scheduled intervals or before power stop. This periodic action ensures data retention without requiring continuous power to all transistors, as the non-volatile portion maintains data during intervals between save operations, reducing power consumption while preserving reliability.
Data Source
AI summary
To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.