Semiconductor Memory Device Voltage Divider Circuit Design
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Solution Overview
Problem
The operating speed of dynamic random access semiconductor memory devices is limited due to the need for two data signals, which increases circuit size and cost, and the voltage drop of one data signal may not be sufficient for accurate sensing before the clock signal disables, reducing system efficiency.
Innovation Solution
A semiconductor memory device with a voltage divider circuit comprising a data line sense amplifier and an input-output data sensing circuit that compares one of two complementary output data signals with a predetermined reference voltage level, reducing necessary sensing time and the number of data signal lines required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If two data signals (IO and ION) are used for data sensing, then data sensing accuracy is improved, but circuit area and device complexity increase
Solution Approach 1:
The patent extracts only one data signal (either IO or ION) for input-output operations, eliminating the need for both complementary signals. The sense amplifier controller selectively enables sensing on a single data line during specific timing periods, reducing circuit complexity while maintaining sensing accuracy through timed voltage level comparison.
Solution Approach 2:
The sense amplifier is designed to handle multiple functions using a single data signal: it can sense both read data and command data by selectively enabling sensing during different timing periods. The same sense amplifier circuit serves dual purposes, reducing the need for separate sensing paths and reducing overall circuit area.
2Measurement precision
If two data signals (IO and ION) are used for data sensing, then data sensing accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts only one data signal (either IO or ION) for input-output operations, eliminating the need for both complementary signals. The sense amplifier controller selectively enables sensing on a single data line during specific timing periods, reducing circuit complexity while maintaining sensing accuracy through timed voltage level comparison.
Solution Approach 2:
The sense amplifier uses the inherent voltage level differences of the single data signal against reference voltages to perform sensing operations. The circuit leverages the natural voltage transitions of the data signal during timing periods to self-determine logic levels without requiring a separate complementary signal for comparison.
3Measurement precision
If voltage sensing is performed during the entire clock period, then data sensing accuracy is improved, but operating speed is limited due to insufficient voltage drop time
Solution Approach 1:
The patent enables the sense amplifier to start sensing operations earlier in the timing period, before the clock signal transitions. By activating sensing during specific timing periods when voltage levels are stable and sufficient time has elapsed for voltage drops, the system achieves accurate sensing without being constrained by clock frequency, thereby improving operating speed.
Solution Approach 2:
The sense amplifier controller dynamically adjusts the sensing enable timing based on the clock signal phase and timing period requirements. The sensing operation is enabled only during appropriate timing windows when voltage levels are suitable for accurate comparison, optimizing both speed and accuracy by adapting to the dynamic voltage transitions of the data signal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the circuit size, increases operating speed, and improves data sensing accuracy by allowing the semiconductor memory device to sense data using only one output data signal, thereby enhancing system efficiency.
Implementation Method 1
The input output data sensing circuit generates a sensed data by comparing voltage levels of the reference output data and the one of the first and the second output data
Data Source
AI summary
The present invention provides a semiconductor memory device, the voltage divider circuit comprises a data line sense amplifier and an input output data sensing circuit. The data line sense amplifier receives a data line signal pair and senses the data line signal pair in a first timing period to generate a first output data and a second output data, wherein, the first output data and the second output data are complementary. The input output data sensing circuit receives at least one reference output data and one of the first and the second output data. The input output data sensing circuit generates a sensed data by comparing voltage levels of the reference output data and the one of the first and the second output data in a second timing period, wherein the voltage level of the reference output data is a pre-determined voltage level.