Semiconductor Memory Device Incremental Voltage Programming

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Solution Overview

Problem

Current semiconductor memory devices face inefficiencies in programming time due to the limitations of traditional program voltage application methods, which do not effectively manage the incremental step pulse program (ISPP) method to optimize memory cell programming operations.

Innovation Solution

The semiconductor memory device employs a control logic to perform a series of program voltage applying operations and verifying operations, incrementally increasing voltages in each step to ensure uniform programming speed across memory cells, using a multi-level program voltage approach that adjusts based on previous operation results.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If traditional program voltage application method is used, then device complexity is reduced, but programming time increases

Engineering Contradiction:
Improveprogramming timeVSAvoidcontrol logic complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The programming operation is divided into multiple incremental steps, each applying a different program voltage level. The control logic segments the voltage application process into distinct stages (first program voltage, second program voltage, third program voltage) with verifying operations between each stage, allowing progressive programming while maintaining control over programming time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The program voltage is dynamically adjusted during the programming process based on verification results. The control logic modifies voltage levels incrementally (first step voltage, second step voltage) depending on whether previous programming attempts succeeded or failed, optimizing programming speed while adapting to actual memory cell states.

Inventive Principle:
Principle #15Dynamics

2Productivity

If incremental step pulse program method is not optimized, then ease of operation is maintained, but productivity decreases

Engineering Contradiction:
Improveprogramming efficiencyVSAvoidoperation simplicity
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The control logic implements feedback mechanisms where verifying operations assess the state of memory cells after each program voltage application. Based on verification results (pass/fail), the system determines whether to proceed to the next voltage level or repeat previous steps, creating a closed-loop control system that optimizes programming efficiency automatically.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The method changes voltage parameters incrementally through defined step voltages (first step voltage, second step voltage) during the programming process. By systematically varying the program voltage parameter based on verification outcomes, the system achieves faster programming without requiring complex manual intervention.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9508438B2Semiconductor memory device, memory system having the same and operating method thereof
Publication Date: 2016.11.29 SK HYNIX INC
  • US9508438B2 patent drawing
  • US9508438B2 patent drawing
  • US9508438B2 patent drawing

AI summary

An embodiment of the invention may provide a semiconductor memory device including a memory cell array including a plurality of memory cells, a peripheral circuit unit configured to perform a program operation with respect to a memory cell selected from the plurality of memory cells, wherein first to third program voltage applying operations and first to third verifying operations are alternatively performed, and a control logic configured to control the peripheral circuit unit to perform the first to third program voltage applying operations and the first to third verifying operations and to increase a second program voltage applied during the second program voltage applying operation more than a first program voltage applied during the first program applying operation by a first step voltage and a third program voltage applied during the third program voltage applying operation more than the second program voltage by a second step voltage.