3D Semiconductor Memory Structure With Wafer Bonding

The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture where the memory array and peripheral drive circuit are arranged in different layers vertically. The memory array is formed on a first substrate while the peripheral drive circuit is formed on a second substrate, with electrical connections established through vertical conductive structures penetrating through the substrates. This dimensional change enables significant reduction in lateral footprint while maintaining manufacturing feasibility through established semiconductor fabrication processes.

The patent divides the NOR flash memory into functionally independent segments: the memory array formed on a first substrate and the peripheral drive circuit formed on a second substrate. These segments can be fabricated simultaneously in parallel using separate fabrication processes, and then bonded together through wafer-level or die-level bonding. This segmentation enables overlapping of fabrication steps, reduces production cycle time, and allows for independent optimization of each segment's manufacturing process.

The patent implements a nested three-dimensional architecture where the peripheral drive circuit is positioned vertically above the memory array, with conductive structures extending downward to establish electrical connections. This nesting arrangement allows both the memory array and peripheral circuit to coexist within a compact volume, effectively increasing the quantity of functional elements integrated in a given footprint while maintaining relatively simple lateral layouts for each individual layer.