Semiconductor Memory Device Wafer Burn-In Static Dynamic Test
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current wafer burn-in tests for semiconductor memory devices primarily perform static tests, failing to include dynamic tests and effectively stress peripheral circuits, limiting the ability to replicate package burn-in tests at the wafer level.
Innovation Solution
A semiconductor memory device and method that enables both static and dynamic tests during wafer burn-in by utilizing a test signal generation block with synchronization and decoding units to generate test commands, addresses, and data, allowing for the testing of word lines and peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If static test is used in wafer burn-in test, then memory cell array can be tested, but dynamic test and peripheral circuit testing cannot be performed
Solution Approach 1:
The address input blocks are designed to serve dual purposes: in normal mode they receive standard address signals for regular memory operations, while in test mode they receive test codes that are synchronized and decoded to generate test commands, test addresses, and test data. This multi-functionality allows the same hardware blocks to support both static and dynamic tests, as well as peripheral circuit testing, without adding separate dedicated test hardware.
Solution Approach 2:
The patent changes the operational parameters of the address input blocks by switching between normal mode and test mode. In test mode, the blocks receive test codes instead of normal addresses, and the synchronization unit processes these codes differently by synchronizing with a test clock to generate test-specific signals. This parameter change enables the system to perform diverse test types using the same hardware infrastructure.
2Reliability
If test signal generation block is added to enable dynamic test, then comprehensive testing is achieved, but device complexity increases
Solution Approach 1:
The test signal generation block merges the functionality of test code reception, synchronization, and decoding into a unified structure that integrates with the existing address input blocks. The synchronization unit and decoding unit are combined within the same test mode operational framework, allowing test commands, addresses, and data to be generated from a single test code input rather than requiring separate control circuits for each test parameter.
Solution Approach 2:
The test code inputted through the address pads serves multiple functions: it is synchronized to generate timing information, decoded to produce test commands, and used to generate test addresses and test data. This self-service approach allows the test code to automatically drive the entire test sequence without requiring external control signals for each test parameter, reducing the need for additional complex control circuitry.
Data Source
AI summary
A semiconductor memory device includes a first address input block which receives first information applied from an exterior as a corresponding normal address in a normal mode and receives the first information as a test clock in a test mode, a second address input block which receives second information applied from an exterior as the corresponding normal address in the normal mode and receives the second information as a test code in the test mode, and a test signal generation block which synchronizes the test code with the test clock in the test mode and generates a test command, a test address and a test data in response to a synchronized test code.