Semiconductor Memory With Wait Signal For Write Cycle
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Solution Overview
Problem
Conventional semiconductor devices, particularly those using dynamic random access memory (DRAM), face challenges in miniaturization due to the difficulty in maintaining necessary electrostatic capacitance, and the writing speed of memory cells with oxide semiconductor transistors limits the operation frequency of microcontrollers (MCUs).
Innovation Solution
A semiconductor device with a memory section that includes a 2T-type gain cell configuration, utilizing an oxide semiconductor transistor as the write transistor and a Si transistor as the read transistor, which allows for delayed access to the memory section by generating a wait signal, thereby increasing the write cycle time and improving operation frequency without being limited by the writing speed of the memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a 1T1C DRAM structure is used for miniaturization, then integration density is improved, but maintaining necessary electrostatic capacitance becomes difficult
Solution Approach 1:
The memory cell is segmented into two transistors and one capacitor (2T1C structure), separating the write function (oxide semiconductor transistor) from the read function (Si transistor). This segmentation allows the capacitor to be optimized for capacitance retention while the write transistor provides efficient charging capability, resolving the contradiction between miniaturization and capacitance maintenance.
Solution Approach 2:
The patent employs a composite transistor structure using two different transistor types (oxide semiconductor transistor and Si transistor) within the same memory cell. The oxide semiconductor transistor provides low leakage and high reliability for data retention, while the Si transistor enables fast read operations. This composite approach allows the memory cell to maintain necessary electrostatic capacitance while achieving miniaturization.
2Reliability
If oxide semiconductor transistors are used in memory cells, then data retention is improved, but writing speed becomes the limiting factor for operation frequency
Solution Approach 1:
Different regions of the memory cell are assigned different transistor types with optimized local qualities: the oxide semiconductor transistor is optimized for data retention with its low leakage characteristics, while the Si transistor is optimized for fast read operations. This local quality differentiation allows the system to achieve both high data retention and high operation frequency without being limited by the writing speed of a single transistor type.
Solution Approach 2:
The patent implements a dynamic memory cell structure where the oxide semiconductor transistor can be selectively activated for write operations and then placed in a low-leakage state for data retention. The ability to dynamically switch between operational modes (write mode with high current drive vs. retention mode with low leakage) allows the system to overcome the writing speed limitation while maintaining high data retention reliability.
3Reliability
If write cycle time is increased to accommodate oxide semiconductor transistor writing speed, then data reliability is improved, but operation frequency is reduced
Solution Approach 1:
The oxide semiconductor transistor is designed with preliminary optimization for low leakage current characteristics before the write operation begins. This preliminary preparation allows the transistor to quickly complete the write operation with high reliability, then immediately transition to a low-leakage retention state. The preliminary optimization of the transistor structure and material properties enables fast write completion without requiring extended write cycle times, thus maintaining high operation frequency while ensuring write completion reliability.
Data Source
AI summary
A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.