Semiconductor Memory Wire Stacking With Overlapping Contacts
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving high integration density and reduced process complexity, particularly in miniaturized circuit patterns.
Innovation Solution
The semiconductor memory device design includes a specific arrangement of wire patterns and gate lines with overlapping contacts and recess capping patterns, enhancing integration density and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-gate transistors are used to increase integration density, then the number of semiconductor memory devices in the same area increases, but the circuit patterns become more miniaturized and process complexity increases
Solution Approach 1:
The patent introduces a vertical dimension by stacking wire patterns (first wire pattern and second wire pattern) at different heights above the substrate. This three-dimensional arrangement allows more wire patterns to be packed in the same planar area, increasing integration density while maintaining manageable process complexity through systematic vertical layering
Solution Approach 2:
The patent divides the circuit interconnection structure into multiple discrete wire patterns (first wire pattern, second wire pattern, third wire pattern, etc.) that can be formed separately at different vertical levels. This segmentation allows each wire pattern to be optimized and formed independently, reducing the overall process complexity despite the increased number of elements
2Quantity of substance
If wire patterns are stacked vertically to increase integration density, then more wire patterns fit in the same area, but the manufacturing process becomes more difficult
Solution Approach 1:
The patent forms sacrificial patterns (first sacrificial pattern and second sacrificial pattern) at different vertical levels before forming the final wire patterns. These sacrificial patterns serve as temporary structures that guide the subsequent wire pattern formation and are removed afterward. This preliminary action simplifies the manufacturing process by providing ready-made templates for the complex three-dimensional wire arrangement
Solution Approach 2:
The sacrificial patterns act as intermediary structures during manufacturing. They are formed first, then used as masks or guides to deposit or etch the wire patterns in specific three-dimensional locations. After serving their mediating function, they are removed, leaving the desired wire pattern structure. This intermediary approach breaks down the complex manufacturing task into simpler, sequential steps
Data Source
AI summary
A semiconductor memory device and a method for manufacturing the same. The semiconductor memory device may include a substrate, a first lower wire pattern and a first upper wire pattern stacked on the substrate, and spaced apart from each other; a second lower wire pattern and a second upper wire pattern stacked on the substrate, spaced apart from each other, and spaced apart from the first lower and upper wire patterns; a first gate line surrounding the first lower wire pattern and the first upper wire pattern; a second gate line surrounding the second lower wire pattern and the second upper wire pattern and spaced apart from the first gate line; a first lower source/drain area; a first upper source/drain area; and a first overlapping contact that electrically connects the first lower source/drain area, the first upper source/drain area and the second gate line to each other.