Semiconductor Memory Device Multi-Layer Wiring and Connection Conductors
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in efficiently connecting bit lines and word lines with high reliability due to their thin dimensions and complex wiring structures, which affects recording density and connection reliability.
Innovation Solution
The semiconductor memory device employs a unique wiring structure with multiple layers of bit and word lines, using connection conductors in virtual planes to connect bit lines and word lines with larger dimensions, ensuring stable connections even with potential misalignment, and utilizing vias to connect layers with reduced risk of direct via misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit lines and word lines are made thinner to increase recording density, then recording density is improved, but connection reliability deteriorates
Solution Approach 1:
The patent transitions from a single-plane wiring structure to a three-dimensional multi-layer wiring structure. Bit lines and word lines are arranged in different layers (first bit line layer, second bit line layer, first word line layer, second word line layer), allowing connections to be established through vertical vias between layers. This dimensional change enables thinner lines in the horizontal plane (increasing density) while maintaining connection reliability through the added vertical dimension.
Solution Approach 2:
The patent introduces connection conductors as intermediary elements between bit lines and word lines. These connection conductors are formed in virtual planes and serve as mediators that connect bit lines from one layer to word lines in another layer. This intermediary structure provides larger connection dimensions and improved alignment tolerance, resolving the contradiction between thin line dimensions and connection reliability.
2Quantity of substance
If wiring structure is made more complex to achieve high-density cross-point arrangement, then recording density is improved, but manufacturing precision requirements worsen
Solution Approach 1:
By distributing bit lines and word lines across multiple layers, the patent reduces the horizontal density requirement, allowing larger via dimensions and more relaxed alignment tolerances. The vertical separation between crossing lines eliminates the need for perfectly aligned vias through the entire stack, as connections are made between adjacent layers only.
Solution Approach 2:
The patent segments the wiring structure into multiple discrete layers (first bit line layer, second bit line layer, first word line layer, second word line layer) with connection conductors in virtual planes between them. This segmentation allows each layer to be manufactured and aligned independently, reducing the cumulative precision requirements compared to a single complex plane.
3Reliability
If connection conductors are used in virtual planes to connect bit lines and word lines, then connection reliability is improved, but device complexity increases
Solution Approach 1:
The connection conductors in virtual planes serve multiple functions: they connect bit lines to word lines, provide alignment tolerance, and enable the three-dimensional cross-point architecture. This multi-functionality justifies the added structural complexity by delivering multiple benefits simultaneously.
Solution Approach 2:
The patent implements a nested wiring structure where connection conductors in virtual planes are embedded within the multi-layer bit line and word line structure. The connection conductors are positioned between the bit line layers and word line layers, creating a nested arrangement that integrates the connection function within the overall wiring architecture rather than adding external complexity.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes: a substrate having a substrate plane extending in a first direction and a second direction intersecting with the first direction; a first wiring provided above the substrate, the first wiring being provided so that a longitudinal direction extends along the first direction; a second wiring provided above the substrate, the second wiring being separated from the first wiring in the first direction, the second wiring being passed by the same virtual line together with the first wiring, the second wiring being provided so that a longitudinal direction extends along the first direction; a third wiring provided between the first wiring and the second wiring, the third wiring being separated from the first wiring and the second wiring, the third wiring being passed by the same virtual line together with the first wiring and the second wiring, the third wiring being provided so that a longitudinal direction extends along the first direction; a fourth wiring provided above the first wiring, the fourth wiring overlapping with the first wiring when viewed from the above, the fourth wiring being provided so that a longitudinal direction extends along the first direction; a fifth wiring provided over the second wiring and the third wiring, the fifth wiring being separated from the fourth wiring in the first direction, the fifth wiring overlapping with the second wiring and the third wiring when viewed from the above, the fifth wiring being passed by the same virtual line together with the fourth wiring, the fifth wiring being provided so that a longitudinal direction extends along the first direction; a sixth wiring provided over the fourth wiring and the fifth wiring, the sixth wiring overlapping with the fourth wiring and the fifth wiring when viewed from the above, the sixth wiring being provided so that a longitudinal direction extends along the first direction; a plurality of seventh wirings provided between the first wiring and the fourth wiring, between the third wiring and the fifth wiring, and between the second wiring and the fifth wiring, the seventh wirings being provided so that a longitudinal direction extends along the second direction; a plurality of eighth wirings provided between the fourth wiring and the sixth wiring and between the fifth wiring and the sixth wiring, the eighth wirings being provided so that a longitudinal direction extends along the second direction; a plurality of first memory cells provided between the first wiring, the second wiring, and the third wiring and the seventh wirings; a plurality of second memory cells provided between the fourth wiring and the seventh wirings and between the fifth wiring and the seventh wirings, the second memory cells overlapping with the first memory cells when viewed from the above; a plurality of third memory cells provided between the fourth wiring and the eighth wirings and between the fifth wiring and the eighth wirings, the third memory cells overlapping with the second memory cells when viewed from the above; a plurality of fourth memory cells provided between the sixth wiring and the eighth wirings, the fourth memory cells overlapping with the third memory cells when viewed from the above; a first connection wiring provided above the substrate, the first connection wiring being provided at least partially under a portion where the first wiring and the third wiring are separated; a second connection wiring provided between the first wiring and the third wiring so that a longitudinal direction extends along a third direction intersecting with the first direction and the second direction, the second connection wiring connecting the sixth wiring and the first connection wiring; a third connection wiring configured to connect the first wiring and the first connection wiring; a fourth connection wiring configured to connect the third wiring and the first connection wiring; a fifth connection wiring provided above the substrate, the fifth connection wiring being provided at least partially under a portion where the second wiring and the third wiring are separated; and a sixth connection wiring provided between the second wiring and the third wiring so that a longitudinal direction extends along the third direction, the sixth connection wiring connecting the fifth wiring and the fifth connection wiring.