3D Semiconductor Memory Device Wiring Coupling via Dielectric Through Parts
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Solution Overview
Problem
Current 3D semiconductor memory devices face challenges in achieving high integration and reliable electrical coupling due to the need for fine-pitch bottom wiring lines, which can lead to increased resistance and signal integrity issues, and require complex patterning of conductive lines for coupling.
Innovation Solution
The semiconductor memory device employs a dielectric structure with through parts that accommodate contact plugs to electrically couple bottom and top wiring lines, eliminating the need for coupling wiring lines and reducing the complexity of conductive line patterning, thereby improving integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine-pitch bottom wiring lines are used to achieve high integration, then integration density is improved, but resistance increases and signal integrity deteriorates
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional wiring structure. Bottom wiring lines are positioned at different vertical levels (first bottom wiring line at lower level, second bottom wiring line at higher level) and connected through contact plugs, effectively utilizing the vertical dimension to reduce pitch constraints and improve signal integrity while maintaining high integration density.
2Reliability
If coupling wiring lines are used to connect bottom wiring lines, then electrical coupling is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the coupling function into the contact plug structure itself. The contact plug serves dual purposes: providing vertical electrical connection between bottom and top wiring lines, and simultaneously acting as the coupling element. This eliminates the need for separate coupling wiring lines, reducing patterning complexity while ensuring reliable electrical coupling.
Solution Approach 2:
The contact plug acts as an intermediary element between bottom wiring lines and top wiring lines. Instead of using complex coupling wiring to directly connect bottom wiring lines, the contact plug mediates the electrical connection, simplifying the overall wiring architecture and reducing manufacturing complexity.
3Quantity of substance
If fine-pitch bottom wiring lines are used, then integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
By utilizing the vertical dimension with multiple wiring layers and contact plugs, the patent reduces the reliance on horizontal pitch reduction. This dimensional transition allows for larger, more manufacturable feature sizes in the horizontal plane while achieving high integration through vertical stacking, thereby reducing manufacturing precision requirements.
Data Source
AI summary
A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over the contact region; a memory block having cell parts which are respectively formed over the cell regions, a coupling part which is formed over the contact region and couples the cell parts, and a through part which accommodates the dielectric structure; a peripheral circuit formed over the substrate under the memory block; bottom wiring lines disposed between the memory block and the peripheral circuit, and electrically coupled with the peripheral circuit; top wiring lines disposed over the memory block; and contact plugs passing through the dielectric structure and coupling the bottom wiring lines and the top wiring lines.