Semiconductor Memory Device Orthogonal Word Line Layout
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Solution Overview
Problem
SRAM semiconductor memory devices with slender memory cells experience increased parasitic resistance and capacitance due to long word line lengths, leading to delayed address access times.
Innovation Solution
The semiconductor memory device employs a layout where the word line is oriented orthogonal to the gate electrodes, reducing the length of the word line and thereby minimizing parasitic resistance and capacitance, allowing for faster address access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the memory array uses a slender memory cell layout with word lines extended in the same direction as gate wiring, then the memory cell area is reduced, but the word line length increases causing increased parasitic resistance and capacitance
Solution Approach 1:
The patent changes the orientation of the word line from parallel to orthogonal relative to the gate electrode, effectively rotating the word line by 90 degrees. This dimensional change allows the word line to extend in a direction perpendicular to the gate wiring, reducing its length while maintaining the slender memory cell layout benefits.
2Object-affected harmful factors
If the word line length is reduced by changing layout orientation, then parasitic resistance and capacitance are minimized, but the memory array shape becomes constrained
Solution Approach 1:
The patent creates an asymmetric layout where the word line extends in a direction orthogonal to the gate electrode, breaking the symmetry of conventional slender memory cell designs. This asymmetric arrangement optimizes the word line length without requiring symmetric adjustments to the entire memory array structure.
Data Source
AI summary
To provide a semiconductor memory device fast in address access time. The semiconductor memory device includes a plurality of memory cells, and a word line coupled to the memory cells. The word line is extended in a first direction. Each of the memory cells includes gate electrodes extended in a second direction intersecting with the first direction.


