Semiconductor Memory Device Word Line Thickness Optimization
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Solution Overview
Problem
Ferroelectric memory devices face degradation of charge retention characteristics due to polarization instability, primarily caused by depolarization electric fields resulting from insulating layers between gate electrodes and semiconductor layers, which hinder the inversion of polarization domains in the ferroelectric layer.
Innovation Solution
The semiconductor memory device employs a three-dimensional NAND flash memory structure with a MFMIS configuration, where the area of the MFM capacitor is made smaller than the MIS capacitor by adjusting the thickness of the word lines and metal layers, thereby weakening the depolarization electric field and improving charge retention. This is achieved by ensuring the thickness of the word line is smaller than the metal layer, with hafnium oxide as the main component in the ferroelectric layers, and maintaining a consistent width of the metal layers to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If insulating layers are provided between gate electrode and semiconductor layer, then electrical isolation is achieved, but depolarization electric field is generated causing polarization instability
Solution Approach 1:
The patent changes the physical parameters of the word line (gate electrode), specifically making its thickness smaller than the metal layer thickness. This parameter change reduces the area of the MFM capacitor relative to the MIS capacitor, thereby weakening the depolarization electric field and improving polarization stability without compromising electrical isolation functionality.
2Force
If word line thickness is increased, then gate control capability is improved, but depolarization electric field strengthens causing polarization instability
Solution Approach 1:
The patent optimizes the word line thickness parameter to be smaller than the metal layer thickness. This creates an asymmetric structure where the gate control capability is maintained through the metal layer while the word line thickness reduction decreases the MFM capacitor area, thereby weakening the depolarization electric field and improving polarization stability.
3Reliability
If MFM capacitor area is reduced, then depolarization electric field is weakened improving charge retention, but gate control efficiency may be compromised
Solution Approach 1:
The patent applies local quality by creating different thickness regions: the metal layer maintains sufficient thickness for effective gate control, while the word line thickness is reduced locally to decrease the MFM capacitor area. This localized parameter differentiation allows simultaneous optimization of both gate control efficiency and charge retention characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively weakens the depolarization electric field, enhances charge retention characteristics, and improves the reliability and power efficiency of the semiconductor memory device, allowing for stable data storage with reduced parasitic capacitance and power consumption.
Implementation Method 1
degradation of charge retention characteristics due to polarization instability
Implementation Method 2
depolarization electric fields resulting from insulating layers between gate electrodes and semiconductor layers
Data Source
AI summary
The semiconductor memory device of the embodiment includes a stacked body including interlayer insulating layers and gate electrode layers alternately stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; a first insulating layer provided between the semiconductor layer and the gate electrode layers; conductive layers provided between the first insulating layer and the gate electrode layers; and second insulating layers provided between the conductive layers and the gate electrode layers and the second insulating layers containing ferroelectrics. Two of the conductive layers adjacent to each other in the first direction are separated by one of the interlayer insulating layers interposed between the two of the conductive layers, and a first thickness of one of the gate electrode layers in the first direction is smaller than a second thickness of one of the conductive layers in the first direction.