Semiconductor Memory Asynchronous Data Write Control
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Solution Overview
Problem
Semiconductor memory devices face issues where they become deactivated during data writing, leading to incomplete data transmission into memory cells due to asynchronous operation with external clock signals.
Innovation Solution
A semiconductor memory device design that maintains operation of the transmission circuit during data writing by using a control circuit to ensure data is written into memory cells even when the chip select signal changes from asserted to negated, utilizing an external clock signal to manage data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the chip select signal changes from asserted to negated during data input period, then the device stops generating internal clock signal to reduce power consumption, but the input data cannot be transmitted to memory cell array resulting in incomplete data writing
Solution Approach 1:
The control circuit detects when the chip select signal changes during the data input period and proactively extends the operation of the transmission circuit beyond the normal data input period. This preliminary action ensures that data already latched in the transmission circuit has sufficient time to be transmitted to the memory cell array even after the chip select signal is negated, preventing incomplete data writing while maintaining power savings.
2Loss of energy
If the transmission circuit operation is stopped immediately when chip select signal is negated, then power consumption is reduced, but data integrity is compromised
Solution Approach 1:
The control circuit monitors the state of the chip select signal and provides feedback control to the transmission circuit. When it detects that the chip select signal changes during the data input period, it extends the transmission circuit operation accordingly. This feedback mechanism ensures data integrity is maintained while minimizing unnecessary power consumption by only extending operation when required.
3Adaptability or versatility
If the device operates asynchronously with external clock signal, then flexibility in operation timing is improved, but control complexity increases to manage data transmission timing
Solution Approach 1:
The control circuit acts as an intermediary between the chip select signal and the transmission circuit operation. It mediates the asynchronous timing by detecting the relationship between the chip select signal transitions and the external clock signal edges, then appropriately controlling the transmission circuit to operate during the necessary period. This intermediary approach manages the timing complexity while preserving asynchronous operation flexibility.
Data Source
AI summary
A semiconductor memory device includes a transmission circuit and a control circuit. The transmission circuit is configured to obtain write data and transmit that into a memory cell array according to the external clock signal when the chip selection signal is asserted. The control circuit is configured to control the transmission circuit to transmit first write data into the memory cell array when the chip selection signal changes from assertion to negation during the input period of the first write data, according to the external clock signal.