Semiconductor Memory Write Sequencing With Pre-Charge Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently executing write operations due to the complexity of controlling multiple memory blocks and transistors, leading to inefficiencies and potential data integrity issues.
Innovation Solution
A semiconductor memory device with a control circuit that executes a first-mode write operation involving sequential pre-charge and program operations, applying specific voltage sequences to select gate lines and word lines to optimize data writing, and a second program operation with voltage switching to enhance data storage reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory blocks and transistors are controlled for write operations, then data storage capacity is improved, but operational complexity increases
Solution Approach 1:
The control circuit divides the write operation into distinct sequential phases: pre-charge phase (charging bit lines to a first voltage level) and program phase (applying program voltage to selected word lines). This segmentation simplifies the control logic by breaking down the complex multi-block write operation into manageable, standardized steps that can be systematically applied across multiple memory blocks.
Solution Approach 2:
The control circuit performs a pre-charge operation before the program operation, charging the bit lines to a predetermined first voltage level. This preliminary action prepares the memory cell transistors in a known state, ensuring that subsequent program operations can be executed reliably across multiple memory blocks without interference from residual charges or uncertain initial conditions.
2Reliability
If sequential pre-charge and program operations are executed, then data integrity is improved, but operation time increases
Solution Approach 1:
The control circuit executes the pre-charge and program operations in continuous sequence without idle periods between them. The program operation immediately follows the pre-charge operation, maintaining continuous useful action on the selected memory cells. This continuous execution ensures data integrity through proper voltage sequencing while minimizing total operation time by eliminating unnecessary delays.
Solution Approach 2:
The control circuit applies voltages in periodic cycles: first charging bit lines to a first voltage level, then applying program voltage to selected word lines, and repeating this sequence for multiple memory blocks. This periodic action pattern ensures that each memory block receives the proper voltage sequence for reliable data writing while maintaining a rhythmic, predictable timing structure that optimizes overall operation speed.
3Manufacturing precision
If voltage sequences are optimized for data writing, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The control circuit changes voltage parameters in a standardized sequence: first setting bit line voltage to a first predetermined level during pre-charge, then applying a second predetermined program voltage level to selected word lines during the program phase. These controlled parameter changes ensure precise voltage application for reliable data writing while using a limited set of standardized voltage levels that simplifies the control circuit design compared to using continuous or numerous discrete voltage levels.
Data Source
AI summary
A semiconductor memory device comprises memory blocks and a control circuit. The control circuit is configured capable of executing a first pre-charge operation and a first program operation, and uninterruptedly thereafter executing a second program operation, in a first-mode write operation. In the first pre-charge operation, a first word line is applied with a certain voltage. In the first program operation, a first select gate line is applied with a first voltage, the first word line is applied with a first program voltage, and a second word line is applied with a write pass voltage smaller than the first program voltage. In the second program operation, a second select gate line is applied with the first voltage, the first word line is applied with a second program voltage larger than the write pass voltage, and the second word line is applied with the write pass voltage.