Semiconductor Memory Write Synchronization via Faster Check-Data Transfer
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Solution Overview
Problem
The introduction of a check module in semiconductor memory to ensure data accuracy slows down read/write speed, negatively affecting performance.
Innovation Solution
A semiconductor memory design that includes a check module generating check data with a shorter transmission time duration than written data, ensuring synchronization and improving write speed by adjusting transmission paths and times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a check module is introduced to check data accuracy, then data read/write reliability is improved, but read/write speed deteriorates
Solution Approach 1:
The patent segments the data writing process into two independent parallel paths: one path transmits written data directly to the data storage unit, while the other path transmits check data to the check bit storage unit. This segmentation allows both data and check data to be written simultaneously without sequential dependency, resolving the contradiction between reliability (check data) and speed (data writing).
Solution Approach 2:
The patent implements preliminary action by pre-calculating check data from the written data before the actual writing operation completes. The check data is generated in advance and transmitted along with the written data, ensuring that data accuracy verification is already prepared before the writing process finishes, thus improving reliability without adding post-write processing delays.
2Ease of operation
If check data is transmitted with the same time duration as written data, then transmission simplicity is improved, but synchronization accuracy deteriorates
Solution Approach 1:
The patent applies parameter changes by adjusting the transmission time duration of check data relative to written data. Specifically, the check data transmission time duration is set to be shorter than that of written data, compensating for the additional processing time required to generate check data from written data. This parameter adjustment ensures that both data types arrive at their respective storage units simultaneously, achieving precise synchronization while maintaining transmission simplicity.
Data Source
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AI summary
A semiconductor memory and a data writing method, the semiconductor memory comprising: at least one storage array which comprises a plurality of data storage units and multiple parity storage units; a check module for receiving write data and generating check data according to the write data; a data transmission module which is connected to the check module and the storage array, and is used for transmitting the write data to the data storage unit and transmitting the check data to the parity storage units. A first transmission duration of the check data is shorter than a second transmission duration of the write data, wherein the first transmission duration is the duration needed for the transmission of the check data from the data transmission module to the parity storage units, and the second transmission duration is the duration needed for the transmission of the write data from the data transmission module to the data storage unit.