Adjustable Power Control Signals for Semiconductor Memory Write Time
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Solution Overview
Problem
Current semiconductor systems face inefficiencies in the read, write, and refresh operations of memory cells due to the fixed overdriving period of bit-line sense amplifiers, which can prolong write times and hinder performance.
Innovation Solution
A semiconductor system with a controller and semiconductor device that generates adjustable power control signals, including a first pulse during write operations and a second pulse after a predetermined time, to optimize the overdriving period of sense amplifiers, allowing for reduced write times by adjusting the power supply period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed overdriving period is used for bit-line sense amplifiers, then the amplifier can reliably sense and amplify bit lines, but the write time is prolonged
Solution Approach 1:
The patent applies dynamics by making the overdriving period adjustable rather than fixed. The control signal generation unit dynamically adjusts the overdriving period based on operation type (read/write/refresh) and test mode signals, allowing the sense amplifier to adapt its power supply duration to different operational requirements, thereby reducing write time while maintaining reliability.
Solution Approach 2:
The patent changes the parameter of overdriving period duration based on different conditions. By receiving test mode signals and adjusting the overdriving period accordingly (shorter for writes, longer for reads/refreshes), the system optimizes performance for each operation type, resolving the contradiction between reliability and write time.
2Productivity
If the overdriving period is shortened to reduce write time, then write speed improves, but sense amplifier performance may deteriorate
Solution Approach 1:
The patent applies local quality by providing different overdriving periods for different operation types. Write operations receive a shorter overdriving period optimized for speed, while read and refresh operations receive longer periods optimized for performance. This localized optimization resolves the contradiction by tailoring the overdriving period to specific operational requirements.
Solution Approach 2:
The system dynamically adjusts the overdriving period based on the operation type and test mode signals. The control signal generation unit selectively extends or reduces the overdriving period, allowing the sense amplifier to operate at optimal performance for each specific operation, thereby improving write speed without compromising overall sense amplifier performance.
3Adaptability or versatility
If test mode signals are added to control overdriving period adjustment, then operational flexibility improves, but device complexity increases
Solution Approach 1:
The control signal generation unit is designed to handle multiple operation types (read, write, refresh) and multiple test modes using a unified structure. By receiving test mode signals and adjusting the overdriving period based on operation type, the single control unit performs multiple functions, achieving operational flexibility without proportionally increasing device complexity.
Data Source
AI summary
A semiconductor system is provided, which includes a controller configured to output an active command and test mode signals; and a semiconductor device configured to sense and amplify a pair of bit lines by generating a first power control signal of which a pulse width is adjusted in accordance with a combination of the test mode signals during an enable period of an enable signal generated by the active command, receiving a supply of a first power according to the first power control signal, and receiving a supply of a second power according to a second power control signal.