Semiconductor Device Mesa Structure Reduces Turn-On Loss
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Solution Overview
Problem
Conventional semiconductor devices, such as insulated gate bipolar transistors (IGBTs), face challenges in improving turn-on loss characteristics.
Innovation Solution
The semiconductor device incorporates a semiconductor substrate with a drift region, featuring gate trench and dummy trench portions, mesa regions, and specific doping concentrations and structures to optimize the accumulation, base, emitter, and intermediate regions, along with varying gate and dummy conductive portions to enhance carrier injection and reduce turn-on losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional IGBT structures are used, then device simplicity is maintained, but turn-on loss characteristics deteriorate
Solution Approach 1:
The device is divided into multiple mesa portions (first mesa portion, second mesa portion, third mesa portion) with different structural configurations. Each mesa portion contains specific regions (accumulation region, base region, emitter region, intermediate region) arranged in different patterns, allowing optimized carrier injection paths while maintaining overall device functionality.
Solution Approach 2:
Different mesa portions have different doping concentrations and region arrangements tailored to their specific functions. The first mesa portion has higher doping concentrations in accumulation and emitter regions for efficient carrier injection, while the second mesa portion has lower doping concentrations for different operational characteristics, optimizing overall turn-on performance.
2Loss of energy
If uniform doping concentrations are used throughout the device, then manufacturing simplicity is maintained, but carrier injection efficiency deteriorates
Solution Approach 1:
The patent implements non-uniform doping concentrations at specific locations: the accumulation region in the first mesa portion has higher doping concentration than the drift region, the emitter region has higher doping concentration than the drift region, while the second mesa portion has lower doping concentrations. This localized doping variation optimizes carrier injection efficiency without requiring complete redesign of the manufacturing process.
Solution Approach 2:
The doping concentration parameter is varied across different regions and mesa portions to optimize device performance. By changing doping concentrations from uniform to non-uniform distributions in specific areas, the patent achieves reduced turn-on loss while maintaining compatibility with existing manufacturing capabilities.
3Loss of energy
If symmetric mesa structures are used, then manufacturing simplicity is maintained, but carrier injection efficiency deteriorates
Solution Approach 1:
The patent employs asymmetric mesa structures where the first mesa portion, second mesa portion, and third mesa portion have different configurations. The first mesa portion contains accumulation, base, and emitter regions with specific doping patterns, while the second mesa portion has different doping concentrations and region arrangements, creating asymmetric carrier injection paths that improve overall turn-on efficiency.
Data Source
AI summary
A semiconductor device including: a drift region formed on a semiconductor substrate; a gate trench portion provided on an upper surface of the semiconductor substrate; a first and second mesa portion adjacent to one and the other of the gate trench portions; an accumulation region provided above the drift region in the first mesa portion; a base region provided above the accumulation region; a emitter region provided between the base region and the upper surface of the semiconductor substrate; an intermediate region provided above the drift region in the second mesa portion; a contact region provided above the intermediate region, wherein the gate trench portion has a gate conductive portion; a bottom portion of the gate conductive portion has a first step and second step; and, at least part of the intermediate region is provided between the steps and the bottom portion of the gate trench portion will be provided.