Semiconductor Mesh Interconnect Layout for Dense Low-Resistance Wiring
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in achieving high integration density while maintaining improved electrical characteristics, as current techniques struggle to form fine patterns efficiently due to the need for advanced exposure methods and high costs.
Innovation Solution
A semiconductor device with an interconnection structure featuring a mesh pattern of first and second interconnection lines, insulating patterns, and a barrier pattern, which are manufactured using a damascene process to enhance electrical connectivity and reduce material diffusion, thereby improving integration density and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If new exposure techniques are used to form fine patterns, then pattern formation capability is improved, but manufacturing cost increases
Solution Approach 1:
The interconnection structure is divided into a mesh pattern consisting of multiple first interconnection lines extending in a first direction and multiple second interconnection lines extending in a second direction intersecting the first direction. This segmentation allows the structure to be formed using conventional exposure techniques rather than requiring advanced fine pattern formation techniques, thereby reducing manufacturing cost while achieving the desired interconnection density
Solution Approach 2:
The patent transitions from traditional planar interconnection patterns to a three-dimensional mesh structure by adding interconnection lines in multiple directions (first direction and second direction) and incorporating insulating patterns that extend into connection regions. This dimensional approach enables improved electrical characteristics and integration density using conventional manufacturing processes
2Productivity
If interconnection line width is reduced to increase integration density, then integration density is improved, but electrical characteristics deteriorate
Solution Approach 1:
The patent creates a mesh interconnection structure with lines extending in multiple directions (first and second directions) and incorporates insulating patterns that extend vertically into the connection regions. This three-dimensional configuration increases the effective conduction path area without reducing the planar footprint, thereby improving electrical characteristics while maintaining high integration density
Solution Approach 2:
The interconnection structure combines conductive interconnection lines with insulating patterns forming a composite mesh structure. The insulating patterns extending into connection regions create a configuration that simultaneously provides electrical conduction pathways and insulation, improving overall electrical characteristics without requiring reduction of interconnection line widths
Data Source
AI summary
A semiconductor device including a lower layer, a plurality of first interconnection lines extending in a first direction on the lower layer, a plurality of second interconnection lines extending in a second direction intersecting the first direction between the first interconnection lines and connecting the first interconnection lines, the second direction intersecting the first direction, first insulating patterns between the second interconnection lines, and second insulating patterns disposed in the first interconnection lines may be provided. The first interconnection lines include connection regions, to each of which at least one of the second interconnection lines is connected. The second insulating patterns extend into the connection regions.