Semiconductor Patterning via Mesh Mask Layer
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Solution Overview
Problem
Current semiconductor patterning methods, such as LELE and SADP, face challenges in increasing pattern density and precision, leading to complex processes and limitations in feature dimension reduction.
Innovation Solution
A patterning method involving the formation of a mesh-shaped mask layer through a series of dielectric layer deposition and etching steps, using intersecting mask structures to create a mesh pattern that increases density and simplifies the process, reducing precision requirements and process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If LELE process is used to increase pattern density, then pattern density is improved, but manufacturing precision requirement becomes extremely high and process complexity increases
Solution Approach 1:
The patent divides the patterning process into multiple stages: first forming a preliminary pattern, then using it as a mask to create a second pattern. This segmentation allows each lithography step to work at relaxed precision requirements while achieving high overall pattern density through the combined effect of multiple patterns.
Solution Approach 2:
The patent introduces an intermediary mask layer that is formed first and then used as a template for the second lithography step. This intermediary structure mediates between the lithography process and the final high-density pattern, enabling density multiplication without requiring the lithography machine to directly achieve the final high precision.
2Quantity of substance
If SADP process is used to make fine patterns, then pattern density is improved, but process complexity increases due to multiple etching steps
Solution Approach 1:
The patent combines the mask formation and pattern transfer steps into a more integrated process. By forming the mask layer once and using it for multiple patterning operations, the method reduces the number of separate etching steps required in conventional SADP, thereby simplifying the overall process while maintaining high pattern density.
3Length of moving object
If feature dimension is reduced to lithography limit, then device miniaturization is achieved, but pattern density multiplication becomes difficult
Solution Approach 1:
The patent transitions from one-dimensional linear patterning to two-dimensional mesh-shaped patterning. By creating intersecting mask structures in perpendicular directions, the method achieves area-based pattern density multiplication rather than relying solely on linear feature size reduction, enabling continued density improvement even when feature dimensions approach lithography limits.
Data Source
AI summary
The present disclosure relates to a patterning method and a method of manufacturing a semiconductor structure. The patterning method includes: providing a base; forming a first patterned mask layer on a surface of the base, where the first patterned mask layer includes a plurality of first mask structures extending along a first direction, and the first mask structures are arranged at intervals; forming a first dielectric layer on the first patterned mask layer, where the first dielectric layer fills up a spacing region between the first mask structures and covers an upper surface of the first patterned mask layer; and etching the first dielectric layer to form a plurality of second mask structures extending along a second direction, where the second mask structures are arranged at intervals, and the second direction intersects with the first direction; and selectively etching the first mask structure and the second mask structure.