Semiconductor Memory Sub-Array Layout for Lower Meta Data ECC Latency
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently storing and managing meta data, leading to increased latency due to the need for generating parity data, especially as memory capacity increases and refresh periods become shorter.
Innovation Solution
A semiconductor memory device design that includes a memory cell array with sub-array blocks, a column access circuit, and separate ECC engines for generating normal and meta parity data, allowing for the storage of meta data and parity data in specific regions of the sub-array blocks, reducing latency by optimizing the generation and storage process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If meta data is stored in semiconductor memory devices with increased memory capacity, then storage capability is improved, but latency increases due to the need for generating parity data
Solution Approach 1:
The memory system is segmented into multiple sub-array blocks, with specific blocks designated for normal data and other blocks for meta data. This segmentation allows parallel processing and storage operations, reducing the latency associated with generating and storing parity data for meta data while maintaining increased memory capacity.
Solution Approach 2:
Parity data for meta data is generated in advance during write operations and stored in dedicated sub-array blocks before read operations occur. This preliminary action eliminates the need to generate parity data during read operations, thereby reducing latency while supporting increased memory capacity.
2Reliability
If separate ECC engines are used for generating normal and meta parity data, then reliability is improved, but device complexity increases
Solution Approach 1:
The ECC functionality is segmented into a main ECC engine for normal data and a sub ECC engine for meta data. This segmentation allows each engine to be optimized for its specific function, improving reliability through specialized error correction while managing complexity by dividing the overall ECC system into modular, independent components.
Solution Approach 2:
The sub ECC engine acts as an intermediary between the main ECC engine and the meta data storage system. It handles the specific task of generating and verifying parity data for meta data, allowing the main ECC engine to focus on normal data operations. This intermediary structure improves overall reliability while keeping each component's complexity manageable.
3Area of stationary object
If meta data and normal data are stored in the same sub-array block, then area utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
Each sub-array block is segmented into distinct regions: one region for normal data and another region for meta data. This physical segmentation within blocks allows efficient area utilization while maintaining clear boundaries that reduce manufacturing precision requirements. The segmented structure ensures that normal data and meta data are stored in separate, well-defined areas within the same block.
Solution Approach 2:
Different regions within sub-array blocks are assigned different local qualities or characteristics optimized for their specific data types. Normal data regions and meta data regions can have different column selection line allocations and ECC engine configurations, allowing each region to be optimized for its purpose while maintaining overall area efficiency and reducing cross-contamination risks during manufacturing.
Data Source
AI summary
A semiconductor memory device includes a memory cell array and a column access circuit. The memory cell array includes a plurality of sub-array blocks and each of the sub-array blocks includes volatile memory cells. The column access circuit receives a plurality of data units, each of which includes normal data and meta data having a ratio of k:1, which is associated with managing the normal data, allocates p column selection lines associated with transferring the data units to the bit-lines to a plurality of normal data and a plurality of meta data in the data units with the ratio of k:1, and stores a sub unit of a first normal data among the plurality of normal data and a sub unit of a first meta data in a first region and a second region of a first sub-array block of the plurality of sub-array blocks, respectively.