Semiconductor Metal Connection Layer for Etching Control
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Solution Overview
Problem
Conventional CMOS image sensor pixel structures face issues with plasma damage to the photosensitive region and over-etching during the formation of sidewall spacers and source/drain contact plugs, leading to damaged pixels and increased leakage current due to the difficulty in controlling the etching process without a metal silicide step.
Innovation Solution
The method involves forming a sidewall spacer on the photosensitive region without etching the sidewall film, and using a metal connection layer as an etching stop during the formation of source/drain contact plugs to prevent over-etching, thereby avoiding plasma damage and leakage current issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a metal silicide step is used to form sidewall spacers, then the etching process can be controlled, but the device complexity increases and manufacturing cost increases
Solution Approach 1:
The patent extracts and removes the metal silicide formation step from the conventional process flow. Instead of forming sidewall spacers through metal silicide deposition and etching, the invention uses a simplified approach where the sidewall spacer is formed directly by depositing a dielectric material and performing a controlled etch-back, eliminating the complex metal silicide intermediary steps while maintaining etching control.
Solution Approach 2:
The patent segments the sidewall spacer formation process into distinct stages: first depositing the dielectric material conformally, then performing selective etching to remove excess material. This segmentation allows precise control over the spacer dimensions without requiring metal silicide, breaking down the complex process into manageable, controllable steps.
2Ease of manufacture
If the sidewall film is etched during sidewall spacer formation, then the etching process can be completed, but plasma damage occurs to the photosensitive region
Solution Approach 1:
The patent applies local quality by making the etching process selective to specific regions. The etching is performed only on the sidewall film in non-photosensitive areas while protecting the photosensitive region through masking or selective etch chemistry. This allows the etching process to complete successfully without causing plasma damage to the photosensitive pixels.
Solution Approach 2:
The patent introduces a protective masking layer or uses selective etch chemistry as an intermediary between the plasma etching process and the photosensitive region. This intermediary protects the photosensitive area from plasma damage while allowing the etching to proceed in other regions, enabling process completion without harmful effects.
3Productivity
If over-etching occurs during source/drain contact plug formation, then the etching process can be completed, but leakage current increases due to damaged pixels
Solution Approach 1:
The patent performs preliminary action by forming a protective layer or establishing precise etch stop conditions before the source/drain contact plug etching. This preliminary preparation ensures that the subsequent etching process stops exactly at the desired depth, preventing over-etching that would damage pixels and cause leakage current, while still allowing complete process execution.
Solution Approach 2:
The patent implements feedback control in the etching process by using real-time monitoring of etch depth or rate, allowing dynamic adjustment of etch parameters. This feedback mechanism prevents over-etching by stopping the process when the predetermined depth is reached, ensuring pixel integrity is maintained while completing the contact plug formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of the CMOS image sensor pixel structure by preventing plasma damage and over-etching, resulting in improved pixel integrity and reduced leakage current.
Implementation Method 1
forming a sidewall spacer on the photosensitive region without etching the sidewall film, and using a metal connection layer as an etching stop during the formation of source/drain contact plugs to prevent over-etching, thereby avoiding plasma damage
Implementation Method 2
using a metal connection layer as an etching stop during the formation of source/drain contact plugs to prevent over-etching
Implementation Method 3
forming a deeply doped region in the photosensitive region of the substrate and containing second doping ions with a type different from the first doping ions; forming a floating diffusion area in the floating diffusion region of the substrate and containing third doping ions with a type different from the first doping ions
Data Source
AI summary
A semiconductor structure is provided and includes: a substrate, containing first doping ions and including a photosensitive region and a floating diffusion region; a deeply doped region, in the photosensitive region of the substrate and containing second doping ions; a floating diffusion area, in the floating diffusion region of the substrate and containing third doping ions; a gate structure on the substrate at a junction of the photosensitive region and the floating diffusion region; a sidewall spacer on the photosensitive region of the substrate, and on sidewalls and top of the gate structure in the photosensitive region; a first doped region located in the floating diffusion area and having fourth doping ions; a metal connection layer on the first doped region; an interlayer dielectric layer on the substrate exposed by the gate structure; and a contact plug, in the interlayer dielectric layer and electrically connected to the metal connection layer.