Semiconductor Control Gate Metal Diffusion Barrier
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Solution Overview
Problem
As semiconductor devices integrate more densely, the diffusion of metal from metal silicide control gates into dielectric patterns can lead to electrical defects, compromising the reliability of flash memory devices.
Innovation Solution
The use of a first conductive pattern with a higher impurity concentration of silicon, followed by a second conductive pattern with lower impurity concentration metal silicide, prevents metal diffusion into the dielectric pattern, thereby enhancing the electric resistance characteristics of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal silicide is used in the control gate to improve electrical resistance characteristics, then the electric resistance characteristic is improved, but metal diffuses into the dielectric pattern during thermal processes causing electrical defects
Solution Approach 1:
A silicon layer is introduced as an intermediary barrier between the metal silicide control gate and the dielectric pattern. This silicon layer prevents metal atoms from diffusing into the dielectric during thermal processes, while still allowing the metal silicide to provide its electrical resistance benefits. The silicon acts as a diffusion barrier that mediates the interaction between the metal silicide and dielectric layers.
Solution Approach 2:
The control gate structure is segmented into multiple layers: a metal silicide layer for electrical resistance control, a silicon layer for diffusion prevention, and a dielectric pattern. This segmentation allows each layer to perform its specific function independently - the metal silicide provides electrical characteristics, the silicon prevents harmful diffusion, and the dielectric provides insulation.
2Productivity
If integration density is increased to improve device capacity, then the device capacity is improved, but the risk of metal diffusion into dielectric patterns increases causing electrical defects
Solution Approach 1:
The silicon layer serves as a protective intermediary that enables higher integration density without increasing the risk of metal diffusion. By placing this diffusion barrier between the metal silicide and dielectric, the structure can be scaled down and densely integrated while maintaining reliability, as the silicon layer continues to prevent metal atoms from contaminating the dielectric patterns.
3Length of moving object
If control gate critical dimension is reduced to improve device scaling, then the device scaling is improved, but metal diffusion becomes more problematic causing higher failure rates
Solution Approach 1:
The silicon intermediary layer becomes increasingly important as the control gate critical dimension is reduced. In scaled-down structures, the proximity between metal silicide and dielectric layers increases, making diffusion more problematic. The silicon layer maintains a protective barrier that prevents metal diffusion even in these tightly scaled structures, enabling successful miniaturization while maintaining low failure rates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the failure rate of erasure and programming operations in semiconductor devices by suppressing metal diffusion, maintaining low failure rates even at smaller critical dimensions of the control gate.
Implementation Method 1
a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration
Implementation Method 2
forming a second conductive pattern including metal silicide by performing a silidation process on the preliminary second conductive pattern and the metal layer
Data Source
AI summary
Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.