Semiconductor Metal Gate with Dual Lateral Widths
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Solution Overview
Problem
In next-generation semiconductor devices, the increasing gate resistance due to miniaturization becomes a critical issue, limiting device performance, as reducing gate metal height to decrease parasitic capacitance increases gate resistance, causing unwanted gate delay.
Innovation Solution
A method involving forming spacers on a semiconductor substrate, recessing a gate metal layer to specific heights, conformally depositing a dielectric layer, and adding a cap layer to reduce gate resistance and capacitance, while maintaining device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the height of gate metal is increased to reduce gate resistance, then gate resistance decreases, but gate to contact parasitic capacitance increases
Solution Approach 1:
The gate metal layer is divided into two portions with different lateral widths. The first portion has a larger lateral width extending beyond the spacers to reduce gate resistance, while the second portion has a smaller lateral width confined between the spacers to reduce parasitic capacitance. This segmentation allows simultaneous optimization of both electrical parameters.
Solution Approach 2:
Different regions of the gate metal layer are given different lateral dimensions to serve different functions. The region extending beyond spacers provides low resistance path, while the region between spacers minimizes capacitance. This local differentiation resolves the contradiction by optimizing each region for its specific purpose.
2Object-generated harmful factors
If the height of gate metal is decreased to reduce gate to contact parasitic capacitance, then parasitic capacitance decreases, but gate resistance increases
Solution Approach 1:
The gate metal layer is segmented into two portions with different lateral extents. The first portion extends beyond the spacers to maintain low gate resistance, while the second portion is confined between spacers to minimize parasitic capacitance. This segmentation enables both capacitance reduction and resistance maintenance.
Solution Approach 2:
Different lateral dimensions are assigned to different regions of the gate metal. The region beyond spacers provides resistance reduction, while the region between spacers provides capacitance reduction. This local quality differentiation resolves the contradiction.
3Reliability
If the lateral width of gate metal is increased to reduce gate resistance, then gate resistance decreases, but device complexity increases
Solution Approach 1:
The complex two-width gate metal structure is formed as a single continuous layer in a preliminary deposition step, before any patterning or etching. This preliminary formation simplifies subsequent processing steps while achieving the desired complex geometry, thereby reducing overall device complexity despite the sophisticated final structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate resistance and capacitance, improving gate delay and overall device performance compared to conventional structures, with a 25% reduction in gate resistance.
Implementation Method 1
conformally depositing a dielectric layer on the at least two spacers and on the recessed first portion of the gate metal layer
Implementation Method 2
conformally depositing a dielectric layer on the at least two spacers and on the recessed first portion of the gate metal layer
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a channel layer on a semiconductor substrate and forming at least two spacers on the channel layer. A first portion of a gate metal layer is formed between the spacers, and a dielectric layer is conformally deposited on the spacers and the first portion of the gate metal layer. In the method, part of the dielectric layer is directionally removed from surfaces which are parallel to an upper surface of the substrate. A second portion of the gate metal layer is formed between remaining portions of the dielectric layer and on the first portion of the gate metal layer, and a cap layer is deposited on the second portion of the gate metal layer. A lateral width the second portion of the gate metal layer is less than a lateral width of the first portion of the gate metal layer.