Semiconductor Metal Gate Height Control via Selective ALD
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor fabrication techniques fail to control the height of the metal gate electrode in MOS transistors due to damage and thickness variations of the interlayer dielectric layer during the removal of the dummy gate electrode.
Innovation Solution
A selective atomic layer deposition process is used to form a sacrificial layer that exposes only the top surface of the dummy gate electrode, allowing for precise control of the metal gate electrode height by protecting the interlayer dielectric layer from etching damage and enabling planarization to match the interlayer dielectric layer's surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the dummy gate electrode is removed using conventional etching techniques, then the metal gate electrode can be formed in the opening, but the interlayer dielectric layer thickness varies and the metal gate electrode height cannot be controlled
Solution Approach 1:
A sacrificial layer is formed on the interlayer dielectric layer before removing the dummy gate electrode. This preliminary action protects the interlayer dielectric layer from etching damage during subsequent processing steps, ensuring consistent thickness and enabling precise control of the metal gate electrode height.
Solution Approach 2:
The sacrificial layer acts as an intermediary protective layer between the etching process and the interlayer dielectric layer. It absorbs the etching damage that would otherwise affect the interlayer dielectric layer, allowing the dummy gate electrode to be removed while maintaining the integrity and consistent thickness of the interlayer dielectric layer.
2Ease of manufacture
If the interlayer dielectric layer is exposed to etching during dummy gate electrode removal, then the dummy gate electrode can be removed, but the interlayer dielectric layer is damaged and its thickness changes
Solution Approach 1:
The sacrificial layer is formed in advance on the interlayer dielectric layer before the etching process. This preliminary protective layer prevents the etching process from damaging the interlayer dielectric layer, ensuring that the dummy gate electrode can be removed cleanly without affecting the underlying interlayer dielectric layer structure.
Solution Approach 2:
The sacrificial layer is designed to be consumed or removed during the etching process. It converts the potentially harmful etching action into a beneficial process by allowing the etching to selectively remove the sacrificial layer and dummy gate electrode while protecting the interlayer dielectric layer from damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively controls the height of the metal gate electrode, preventing interlayer dielectric layer thickness changes and ensuring consistent semiconductor device fabrication.
Implementation Method 1
forming a sacrificial layer covering a top surface of the interlayer dielectric layer by using a selective atomic layer deposition process
Data Source
AI summary
A method is provided for fabricating a semiconductor device. The method includes providing a base substrate including a dummy gate electrode and an interlayer dielectric layer covering a sidewall of the dummy gate electrode. The method also includes forming a sacrificial layer covering a top surface of the interlayer dielectric layer by using a selective atomic layer deposition process, wherein the sacrificial layer exposes a top surface of the dummy gate electrode. In addition, the method includes forming an opening by using the sacrificial layer as an etch mask to remove the dummy gate electrode, and forming a metal gate electrode on the sacrificial layer and in the opening. Further, the method includes planarizing the metal gate electrode and the sacrificial layer until a top surface of the metal gate electrode is leveled with the top surface of the interlayer dielectric layer.