Semiconductor Device Metal Gate Formation Using Helmet Layer
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in forming semiconductor structures with precise control over trench isolation and metal gate formation, leading to inefficiencies in the formation of FinFETs, particularly in reducing the height loss of interlayer dielectric during the cut metal gate process, which can damage epitaxially grown semiconductor material and limit process windows.
Innovation Solution
The method involves forming a helmet layer over recessed interlayer dielectric and gate spacers, polishing it to create concave surfaces, and using a patterned hard mask to selectively remove metal gate stacks and gate spacers, allowing for precise control of opening formation with reduced interlayer dielectric loss and expanded process windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication techniques are used for metal gate formation, then the process is simpler, but interlayer dielectric loss increases and damage to epitaxially grown semiconductor material occurs
Solution Approach 1:
The method performs preliminary actions by forming a helmet layer over the interlayer dielectric and gate spacers before the cut metal gate etching process. This helmet layer is then selectively removed to define the etching pattern, preventing excessive interlayer dielectric loss and protecting epitaxially grown semiconductor material from damage during the etching process.
2Reliability
If conventional etching processes are used, then the process window is narrower, but the fabrication steps are fewer
Solution Approach 1:
The patent introduces a helmet layer as an intermediary structure that mediates between the interlayer dielectric and the etching process. This helmet layer serves as a protective mediator during etching, expanding the process window by providing a buffer that prevents direct excessive etching of the interlayer dielectric and protects underlying epitaxially grown semiconductor material.
3Manufacturing precision
If precise control over trench isolation and metal gate formation is achieved, then manufacturing precision improves, but the number of fabrication steps increases
Solution Approach 1:
The fabrication process is segmented into distinct functional stages: forming the helmet layer over the interlayer dielectric and gate spacers, selectively removing portions of the helmet layer to define the metal gate pattern, and using this patterned helmet layer to control the subsequent etching process. This segmentation allows precise control over trench isolation and metal gate formation while organizing the increased number of fabrication steps into manageable, functionally distinct operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces interlayer dielectric loss, prevents damage to epitaxially grown semiconductor material, and expands the process window for subsequent CMG etching, enhancing the precision and efficiency of semiconductor device fabrication.
Implementation Method 1
polishing it to create concave surfaces
Implementation Method 2
performing an etch process on the portions of the metal gate, the capping structure, and the dielectric layer that are aligned vertically with the opening of the patterned hard mask
Data Source
AI summary
A method of forming a semiconductor device includes removing a top portion of a dielectric layer surrounding a metal gate to form a recess in the dielectric layer; filling the recess with a capping structure; forming a patterned hard mask over the capping structure and over the metal gate, wherein a portion of the metal gate, a portion of the capping structure, and a portion of the dielectric layer are aligned vertically with an opening of the patterned hard mask; and performing an etch process on said portions of the metal gate, the capping structure, and the dielectric layer that are aligned vertically with the opening of the patterned hard mask, wherein the capping structure has an etch resistance higher than an etch resistance of the dielectric layer during the etch process.