Semiconductor Metal Gate Planarization with Protective Slurry
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Solution Overview
Problem
The increasing leakage current in semiconductor devices due to the decreasing thickness of conventional gate dielectric layers leads to issues like increased power consumption, and the CMP process used to form metal gates damages device layers in other regions, causing defects and contamination.
Innovation Solution
A method involving a semiconductor substrate with distinct regions, where a dummy gate is formed and removed to create a trench, and a metal layer is planarized using a polishing slurry with a protective agent to form a gate electrode while preventing damage to device layers by forming a protective layer during the planarization process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a CMP process is used to planarize the metal layer to form the metal gate, then the metal gate can be formed with a flat surface, but the device layers in other regions are damaged and defects such as polishing dishes are formed
Solution Approach 1:
The chip is divided into a core region and a peripheral region, with different gate structures formed in each region. The core region uses HKMG structure with metal gate and high-K dielectric layer, while the peripheral region maintains conventional polysilicon gate structure. This segmentation allows the CMP process to be optimized for the metal gate region without damaging the polysilicon device layers in the peripheral region.
Solution Approach 2:
A dummy gate structure is introduced as an intermediary element in the core region. The dummy gate includes a dummy gate dielectric layer and a dummy gate electrode layer that is removed later. This dummy structure allows the high-K dielectric layer to be formed and planarized without directly exposing the metal gate to the CMP process, thereby preventing damage to the metal layer and enabling better control of the planarization process.
2Productivity
If the thickness of the conventional gate dielectric layer is decreased to increase integration level, then the integration level increases, but the leakage current of the gate electrode increases
Solution Approach 1:
The dielectric material parameter is changed from conventional silicon oxide to high-K dielectric material (such as HfO2, HfSiO, or HfSiON). This parameter change allows the dielectric layer to maintain very thin thickness (enabling high integration) while providing sufficiently high breakdown voltage to prevent gate leakage current, thus resolving the contradiction between thinning the gate dielectric and preventing leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces damage to device layers during planarization, maintaining their performance and preventing defects, thereby addressing the leakage current issues and power consumption concerns.
Implementation Method 1
planarizing the metal layer by a chemical mechanical polishing (CMP) process to form a metal gate
Data Source
AI summary
A method for fabricating a semiconductor structure includes providing a semiconductor substrate having a first region and a second region; and forming a first dummy gate on the semiconductor substrate in the first region and a device layer on the semiconductor substrate in the second region. The method also includes forming a dielectric layer on of the first dummy gate and the device layer; and removing the first dummy gate to form a first trench. Further, the method includes forming a first metal layer on the first trench and the surfaces of the dielectric layer and the device layer; and performing a first planarization process onto the first metal layer using a polishing slurry having a first protective agent to form a first gate electrode in the first trench and form a protective layer on the device layer preventing the device layer being damaged during the first planarization process.