Semiconductor Device Metal Gate Wiring Layer Height Difference

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Solution Overview

Problem

The use of polysilicon between electrodes and wires in semiconductor devices leads to height differences, reducing machining accuracy and increasing variation in IGBT characteristics.

Innovation Solution

A semiconductor device design featuring a metal gate wiring layer that extends from the outer periphery towards the central portion, directly connected to the gate electrode without polysilicon interposition, along with a lattice-shaped gate trench structure and dummy trench portions, to improve electrical connectivity and reduce height differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If polysilicon is provided between the gate electrode and the gate wiring layer, then electrical connection is achieved, but a height difference occurs that reduces machining accuracy and increases variation in IGBT characteristics

Engineering Contradiction:
Improveelectrical connectionVSAvoidmachining accuracy
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The invention removes the polysilicon layer from between the gate electrode and the gate wiring layer, extracting the source of the height difference problem. The gate wiring layer is now in direct contact with the gate electrode, eliminating the polysilicon-induced height variation while maintaining electrical connection through the metal-to-metal or metal-to-semiconductor interface.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention changes the material parameter of the connection layer from polysilicon to direct metal contact. By altering the material composition and interface structure, the height difference parameter is reduced, thereby improving machining accuracy and reducing IGBT characteristic variation while preserving electrical connectivity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If polysilicon is used to connect the gate electrode and gate wiring layer, then electrical connectivity is established, but the height difference causes greater variation in IGBT characteristics

Engineering Contradiction:
Improveelectrical connectivityVSAvoidIGBT characteristics uniformity
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The polysilicon layer is extracted from the connection structure, removing the source of height variation that causes IGBT characteristic differences. The direct contact between the gate wiring layer and gate electrode ensures uniform electrical connectivity across all IGBT devices, improving characteristic uniformity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

By eliminating the polysilicon layer, the invention creates a more homogeneous interface structure between the gate wiring layer and gate electrode. This uniformity in the connection structure reduces variations in electrical properties across different IGBT devices, leading to more consistent characteristics.

Inventive Principle:
Principle #33Homogeneity

Data Source

PatentUS10529814B2Semiconductor device
Publication Date: 2020.01.07 FUJI ELECTRIC CO LTD
  • US10529814B2 patent drawing
  • US10529814B2 patent drawing
  • US10529814B2 patent drawing

AI summary

Machining accuracy of an IGBT region is worsened due to a height difference caused by polysilicon. Therefore, there is a problem that characteristic variation of the IGBT increases. Provided is a semiconductor device including a semiconductor substrate; a gate wiring layer provided on a front surface side of the semiconductor substrate; and a gate structure that includes a gate electrode and is provided on the front surface of the semiconductor substrate. The gate wiring layer includes an outer periphery portion that is a metal wiring layer and is provided along an outer periphery of the semiconductor substrate; and an extending portion that is a metal wiring layer, is provided extending from the outer periphery portion toward a central portion of the semiconductor substrate, and is electrically connected to the gate electrode.