Semiconductor Metal Layer Bin Sizing for IC Resource Planning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity and density of semiconductor integrated circuits (ICs) lead to prolonged design cycle times and resource inefficiencies in the design and fabrication process, particularly due to the challenges in resource planning across metal layers with disparate properties, which compromises modeling accuracy and computational burden.
Innovation Solution
An improved bin-based resource planning methodology is introduced, where individual metal layers are assigned optimized bin sizes based on their layout properties and circuit geometry, allowing for more accurate modeling and reduced computational effort.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform bin size is used for all metal layers, then the resource planning process is simplified, but modeling accuracy deteriorates due to disparate layout properties across layers
Solution Approach 1:
The patent applies local quality by assigning different bin sizes to different metal layers based on their specific layout properties. Each metal layer receives a customized bin size that matches its density and complexity characteristics, rather than using a uniform bin size across all layers. This resolves the contradiction by maintaining simplicity in the overall process while achieving high accuracy through localized optimization.
2Measurement precision
If smaller bin sizes are used for all layers, then modeling accuracy improves, but computational burden increases significantly
Solution Approach 1:
The patent changes the parameter of bin size from a fixed uniform value to variable values optimized for each metal layer. By adjusting bin size parameters according to layer-specific properties such as density and complexity, the system achieves high modeling accuracy without applying uniformly small bins across all layers, thus avoiding excessive computational burden.
3Productivity
If larger bin sizes are used for all layers, then computational time is reduced, but modeling accuracy deteriorates and manual corrections are required
Solution Approach 1:
The patent applies local quality by matching bin sizes to the specific characteristics of each metal layer. Layers with simpler layouts use larger bins for faster processing, while layers with higher density and complexity use appropriately smaller bins to maintain accuracy. This localized optimization resolves the contradiction by achieving both computational efficiency and modeling accuracy simultaneously.
4Manufacturing precision
If resource planning is performed with high accuracy, then design quality is improved, but design cycle time increases
Solution Approach 1:
The patent changes the bin size parameter dynamically based on metal layer properties, enabling the resource planning process to achieve high design quality through optimized modeling without uniformly increasing computational effort across all layers. This parameter optimization resolves the contradiction by maintaining high accuracy where needed while reducing unnecessary computational overhead elsewhere.
Data Source
AI summary
A method includes: accessing a design data of an integrated circuit (IC), wherein the design data includes a transistor layer and a plurality of metal layers over the transistor layer; assigning a bin size for each of the metal layers based on layout properties of the respective metal layers, wherein a bin size of a higher larger of the metal layers has a greater bin size than that of a lower layer of the metal layers; performing resource planning on the transistor layer and each of the metal layers according to the assigned bin sizes of the respective metal layers; and updating the design data according to the resource planning. At least one of the accessing, assigning, performing and updating steps is conducted by at least one processor.