Semiconductor Package Metal Layer Interposer for EMI Shielding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor package technologies face challenges in achieving high integration density and reliability while maintaining a small size, often requiring complex processes and being prone to electromagnetic interference and manufacturing complexity.
Innovation Solution
The semiconductor package design includes a wiring board with flip-chip mounted semiconductor chips, a metal layer with a recessed portion for the second chip, and isolated ground interconnections to minimize interference and simplify manufacturing, featuring a package-on-package structure with reduced thickness and bonding wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are integrated in a limited area to increase memory capacity, then high integration density is achieved, but manufacturing precision requirements increase and electromagnetic interference occurs
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by placing a second semiconductor chip above a first semiconductor chip, separated by a metal layer. This vertical arrangement achieves high integration density without requiring extremely precise lateral positioning, thereby resolving the contradiction between integration density and manufacturing precision requirements
Solution Approach 2:
The patent divides the package into multiple stacked layers (first semiconductor chip, metal layer, second semiconductor chip) with each layer serving specific functions. This segmentation allows independent optimization of each layer and reduces the overall precision requirements compared to monolithic high-density integration
2Quantity of substance
If multiple semiconductor chips are integrated to increase capacity, then memory capacity increases, but electromagnetic interference between chips occurs
Solution Approach 1:
A metal layer is introduced as an intermediary between the first and second semiconductor chips. This metal layer serves as a shielding barrier that blocks electromagnetic interference between the chips while allowing the package to maintain high integration capacity through vertical stacking
Solution Approach 2:
The harmful electromagnetic interference is extracted and blocked by the metal layer positioned between the semiconductor chips. The metal layer specifically targets and removes the electromagnetic interference problem while preserving the beneficial high-capacity integration
3Quantity of substance
If complex integration techniques are used to achieve high capacity, then memory capacity increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
By moving to three-dimensional stacking architecture, the patent achieves high capacity with simpler processes compared to planar high-density integration. The vertical arrangement naturally separates signal paths and reduces cross-talk, simplifying the overall device design and manufacturing
4Length of stationary object
If three-dimensional stacked structure is used to reduce package thickness, then package size decreases, but manufacturing precision requirements increase
Solution Approach 1:
The metal layer is designed with selective width characteristics - wider than the first semiconductor chip in some regions and providing specific coverage in others. This local variation in metal layer dimensions optimizes both the shielding effectiveness and the alignment tolerance, allowing thickness reduction without excessive precision requirements
Data Source
AI summary
Semiconductor packages are provided. A semiconductor package may include a wiring board and a first semiconductor chip on the wiring board. Moreover, the semiconductor package may include a metal layer on the first semiconductor chip and a second semiconductor chip on the metal layer. The metal layer may be between the first and second semiconductor chips.