Semiconductor Metal Layer Overlap for High-Voltage Reliability
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Solution Overview
Problem
As ultra-high voltage semiconductor devices scale down, it becomes challenging to achieve high breakdown voltage, low specific on-resistance, and high reliability in both room temperature and high temperature environments.
Innovation Solution
A semiconductor device design featuring a substrate with a high-voltage well and source well, an isolation layer, a gate layer that continuously extends from the source well to the isolation layer, and a metal layer with specific overlapping portions to enhance conductivity and contact areas, facilitating high-voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If device dimensions are scaled down, then device size is reduced, but breakdown voltage and reliability deteriorate
Solution Approach 1:
The patent applies local quality by creating a continuously extending gate layer that provides enhanced electric field control specifically at critical regions (source well edges and isolation layer interfaces) while maintaining standard device dimensions elsewhere. This localized enhancement of gate control in high-stress areas allows the device to achieve high breakdown voltage without increasing overall device size.
Solution Approach 2:
The patent transitions from conventional planar gate structures to a three-dimensional continuously extending gate layer that wraps around source well edges and extends to isolation layer edges. This dimensional change creates additional control surfaces and improves electric field management in vertical and lateral directions simultaneously, enabling high breakdown voltage in scaled devices.
2Volume of moving object
If device dimensions are scaled down, then device size is reduced, but specific on-resistance increases
Solution Approach 1:
The metal layer configuration provides localized conductivity enhancement at critical regions including source region contacts and gate layer contacts. The first metal portion overlapping the source region and second metal portion contacting the gate layer create low-resistance pathways specifically where needed, reducing specific on-resistance without increasing overall device footprint.
Solution Approach 2:
The patent employs a composite metal layer structure with multiple metal portions having different functions and positions. The combination of metal portions overlapping source regions, contacting gate layers, and extending to isolation edges creates a composite conductive system that optimizes both conductivity and electric field control, achieving low specific on-resistance in scaled devices.
3Reliability
If gate layer is extended to improve breakdown characteristics, then breakdown voltage improves, but device complexity increases
Solution Approach 1:
The patent merges multiple gate functions into a single continuously extending gate layer that simultaneously performs channel control, edge field management, and isolation region control. This unified structure eliminates the need for separate gate components, improving breakdown characteristics while actually reducing device complexity compared to multi-component approaches.
Data Source
AI summary
A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate, a source well having the first conductivity type and formed in the high-voltage well, a source region formed in the source well, an isolation layer formed above the high-voltage well and spaced apart from the source well, a gate layer formed above the substrate and continuously extending from above an edge portion of the source well to an edge portion of the isolation layer, and a metal layer formed above the substrate and the isolation layer. The metal layer includes a first metal portion overlapping an edge portion of the gate layer and a side portion of the isolation layer, a second metal portion overlapping and conductively contacting the gate layer, and a third metal portion overlapping and conductively contacting the source region.