Patterned Semiconductor Metal Layer Warpage Control
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Solution Overview
Problem
The warpage of semiconductor substrates due to thickness or material differences between metal layers on the front and back surfaces leads to crack generation and voids in solder, affecting assemblability, and existing stress mitigation methods require heat treatment, which degrades solder wettability.
Innovation Solution
A semiconductor device design where the second metal layer for soldering on the front surface is thicker and patterned, with the first, third, and fourth metal layers not patterned, allowing stress absorption through gaps and preventing oxidation, thereby improving assemblability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If metal layers for soldering are formed on both front and back surfaces of a semiconductor substrate, then low power loss and size reduction are achieved, but substrate warpage occurs due to stress from thickness or material differences between metal layers
Solution Approach 1:
The second metal layer on the front surface is divided into a pattern of multiple segments, while the third and fourth metal layers remain as continuous films. This segmentation allows the front surface metal layer to better accommodate thermal expansion and contraction stresses, reducing the overall warpage of the substrate while maintaining the low power loss benefits of dual-sided soldering.
2Manufacturing precision
If metal layers are made thinner to reduce chip cost, then electrical characteristics improve and unit price decreases, but substrate warpage becomes more evident
Solution Approach 1:
The patent employs asymmetric design where the second metal layer on the front surface is patterned into segments while the third and fourth metal layers on the back surface remain as continuous films. This asymmetric configuration compensates for the increased warpage susceptibility of thinner substrates by creating a stress distribution that counteracts warpage while maintaining favorable electrical characteristics.
3Shape
If heat treatment is applied to crystallize metal films for soldering, then stress is counteracted and warpage is suppressed, but solder wettability deteriorates due to oxidation
Solution Approach 1:
The second metal layer is designed with a patterned structure from the beginning, before assembly and soldering processes. This preliminary patterning enables the metal layer to inherently manage thermal stress and reduce warpage without requiring subsequent heat treatment, thereby preserving the solder wettability and avoiding oxidation-related deterioration.
4Stability of the object's composition
If metal layers are made thicker to reduce warpage, then substrate stability improves, but manufacturing complexity and cost increase
Solution Approach 1:
Instead of uniformly increasing the thickness of all metal layers, the patent segments the second metal layer into a patterned configuration. This segmentation provides the stress management benefits of thicker metal layers for warpage reduction, while the patterned design actually reduces material usage and manufacturing complexity compared to solid thick layers, thereby improving substrate stability without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Minimizes substrate warpage and maintains solder wettability by absorbing thermal stress without the need for heat treatment, enhancing assembly reliability.
Implementation Method 1
The stress generated when the thick second metal layer expands or contracts due to a temperature change is therefore absorbed by the gaps in the pattern.
Data Source
AI summary
A semiconductor substrate (1) has a front surface and a back surface that are opposite each other. A first metal layer (2) is formed on the front surface of the semiconductor substrate (1). A second metal layer (3) for soldering is formed on the first metal layer (2). A third metal layer (5) is formed on the back surface of the semiconductor substrate (1). A fourth metal layer (6) for soldering is formed on the third metal layer (5). The second metal layer (3) has a larger thickness than that of the fourth metal layer (6). The first, third, and fourth metal layers (2,5,6) are not divided in a pattern. The second metal layer (3) is divided in a pattern and has a plurality of metal layers electrically connected to each other via the first metal layer (2).