Semiconductor Package Metal Layer Stress Reduction
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Solution Overview
Problem
Semiconductor packages face challenges with warpage due to differential thermal stress during fabrication and operation, which affects their reliability and performance, especially as they become smaller and more complex.
Innovation Solution
A semiconductor package design that includes a lower package with a metal layer on the lower semiconductor chip, a ground member coupled to the metal layer, and an upper package with a ground pattern exposed through a hole in the insulation pattern, which helps to absorb stress and prevent warpage by grounding the metal layer, thereby enhancing reliability and shielding against electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor package dimensions are reduced to achieve miniaturization, then the package size is reduced, but warpage of the semiconductor package increases
Solution Approach 1:
The patent divides the semiconductor package into distinct layers including a lower package, upper package, and intermediate metal layer. This segmentation allows each layer to be independently designed and controlled, enabling the metal layer to specifically address warpage through stress compensation without affecting the overall miniaturization of the package structure.
Solution Approach 2:
The patent introduces a metal layer with specific physical properties (high thermal conductivity, appropriate thickness of 1-10 μm) between the lower and upper packages. By changing the material parameters and structural configuration, the metal layer compensates for differential thermal stress and reduces warpage while maintaining the reduced package dimensions.
2Stability of the object's composition
If a metal layer is added to reduce warpage, then warpage is reduced, but device complexity increases
Solution Approach 1:
The metal layer serves multiple functions simultaneously: it acts as a stress compensation layer to reduce warpage, provides electromagnetic shielding between the lower and upper packages, and functions as a ground reference plane. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity while effectively addressing warpage.
Solution Approach 2:
The patent combines the warpage reduction function with electromagnetic shielding and grounding functions into a single metal layer structure. By merging these functions, the patent avoids adding separate complex subsystems, thus reducing warpage while minimizing the increase in overall device complexity.
3Reliability
If the metal layer is grounded to prevent electrostatic discharge, then reliability is improved, but device complexity increases
Solution Approach 1:
The metal layer is designed to serve as both a structural element for warpage control and an electrical ground reference. By making the metal layer electrically conductive and connecting it to ground, the patent achieves electrostatic discharge protection without requiring a separate grounding structure, thus improving reliability while minimizing increases in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces warpage and enhances the reliability of semiconductor packages by grounding the metal layer, preventing damage from electrostatic discharge and improving electromagnetic interference shielding, thus ensuring stable operation and increased performance.
Implementation Method 1
differential thermal stress during fabrication and operation
Implementation Method 2
grounding the metal layer, thereby enhancing reliability and shielding against electromagnetic interference
Implementation Method 3
metal shield is between the first package and the second package and is attached to the first package with an adhesive. The metal shield is electrically connected to a ground potential
Data Source
AI summary
A semiconductor package comprises a lower package, a metal layer on the lower package, a ground member on the metal layer, coupled thereto, and an upper package on the lower package. The upper package comprises a ground pattern on a first insulation pattern. The first insulation pattern is on a bottom surface of the upper package and has a hole through which the ground pattern is exposed. The ground member extends inside the hole and is coupled to the ground pattern.