Semiconductor Metal Line Scratch Prevention via Protective Film
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Solution Overview
Problem
High ductility of metal lines in semiconductor devices, particularly copper, leads to scratches during the chemical mechanical polishing (CMP) process, causing notches in subsequent interlayer insulation layers and resulting in metal shorts, which degrade the yield of semiconductor devices.
Innovation Solution
A semiconductor device manufacturing method that includes forming a substrate with a first interlayer insulation layer and a first metal line, followed by a CMP process to planarize the metal line, then forming additional interlayer insulation layers with etch stop layers and insulation layers to prevent scratch transfer, and finally forming separated second metal lines through further CMP processes to avoid notch formation and shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper metal lines are used due to high ductility, then electrical conductivity is improved, but scratches occur during CMP process causing notches and shorts
Solution Approach 1:
A protective film is introduced as an intermediary layer between the copper metal line and the CMP polishing head. This protective film prevents direct contact and friction between the polishing head and copper surface, thereby preventing scratch formation during CMP while allowing the copper to maintain its excellent electrical conductivity properties
Solution Approach 2:
The protective film is formed on the copper metal line surface before the CMP process is performed. This preliminary protective coating ensures that when the CMP process occurs, the copper surface is already protected from mechanical damage, preventing scratches and subsequent notches in the interlayer insulation layer
2Manufacturing precision
If CMP process is used to planarize metal lines, then surface flatness is improved, but scratches are formed on high ductility metals
Solution Approach 1:
The protective film serves as a mediator that enables the CMP process to achieve surface flatness without directly exposing the copper to the polishing head. The film absorbs the mechanical stress and friction, allowing planarization to occur while preventing scratch generation on the underlying metal surface
Solution Approach 2:
The protective film is designed to be removed or patterned after CMP, converting the potential harm of additional processing steps into a benefit by enabling scratch-free planarization. The film's temporary presence during CMP transforms a complex multi-step process into an effective solution for achieving flat surfaces without scratches
3Reliability
If notches form in interlayer insulation layer due to scratches, then metal shorts occur, but yield is degraded
Solution Approach 1:
The protective film is applied to the copper metal line surface before the CMP process, preventing scratch formation at the source. This preliminary protection ensures that when the interlayer insulation layer is subsequently formed, no notches are created that could lead to metal shorts, thereby maintaining high manufacturing yield
Solution Approach 2:
The protective film provides preliminary anti-action against the scratch-forming mechanism during CMP. By preventing the initial scratch formation on the copper surface, the film proactively counteracts the chain of events that would lead to notches in the interlayer insulation layer and subsequent metal shorts, preserving device yield
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents the transfer of scratches and notches, ensuring flat surfaces and preventing metal shorts between lines, thereby enhancing the yield and reliability of semiconductor devices.
Implementation Method 1
a first chemical mechanical polishing (CMP) process is performed of planarizing the first metal line and the first interlayer insulation layer
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed. The semiconductor device also includes a first via plug and a first metal line respectively formed by filling the first via hole and the first trench with a first metal, a predetermined scratch being formed on the first metal line; and a second via plug a second metal line respectively formed by filling a second via hole and a second trench with a second metal, the second metal lines being separated.