Gate-All-Around Semiconductor Structure with Metal Oxide Dopant Barrier
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Solution Overview
Problem
Conventional methods for manufacturing gate-all-around (GAA) devices face challenges as they are scaled down, leading to issues such as dopant out-diffusion, threshold voltage variation, increased minimum operating voltage, drain-induced barrier lowering, larger subthreshold leakage current, and degraded carrier mobility.
Innovation Solution
The implementation of metal oxide layers, specifically rare earth oxides like lanthanum oxide, gadolinium oxide, or yttrium oxide, is used to retard or block dopants from diffusing into the channel regions of GAA devices, thereby improving the mobility and performance of SRAM and logic cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If GAA devices are scaled down to reduce chip footprint, then device density increases, but dopant out-diffusion into channel regions worsens
Solution Approach 1:
A metal oxide layer is introduced as an intermediary barrier between the doped source/drain regions and the channel region. This metal oxide layer prevents dopant atoms from diffusing into the channel while allowing the device to maintain its scaled-down dimensions, thus resolving the contradiction between miniaturization and dopant diffusion control.
Solution Approach 2:
The device structure employs composite materials including metal oxide layers combined with semiconductor materials. This composite structure provides both the electrical functionality required for scaled-down operation and the physical barrier needed to prevent dopant out-diffusion, simultaneously achieving small footprint and precise dopant control.
2Device complexity
If conventional manufacturing methods are used for scaled-down GAA devices, then manufacturing simplicity is maintained, but threshold voltage stability deteriorates
Solution Approach 1:
The metal oxide layer serves as a stabilizing intermediary that prevents dopant contamination of the channel region. This simple addition of a barrier layer significantly improves threshold voltage stability without requiring complex manufacturing process changes, thus resolving the contradiction between manufacturing simplicity and voltage stability.
3Productivity
If GAA devices are scaled down, then production efficiency increases, but subthreshold leakage current increases
Solution Approach 1:
The harmful dopant atoms are effectively extracted or blocked from entering the channel region by the metal oxide barrier. This prevents the formation of high doping concentrations in the channel that would cause increased subthreshold leakage, allowing scaled-down devices to maintain low leakage currents while benefiting from high production efficiency.
4Ease of manufacture
If conventional methods are used for scaled-down GAA devices, then manufacturing cost is controlled, but carrier mobility degrades
Solution Approach 1:
The metal oxide layer acts as a protective intermediary that prevents dopant-induced degradation of the channel region. By blocking dopant diffusion, it preserves the high carrier mobility of the undoped channel while adding minimal complexity to the manufacturing process, thus maintaining cost-effectiveness while improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of metal oxide layers results in improved threshold voltage stability, reduced subthreshold leakage current, enhanced carrier mobility, and lower minimum operating voltage for GAA devices, effectively addressing the scaling challenges faced by conventional methods.
Implementation Method 1
metal oxide layers, specifically rare earth oxides like lanthanum oxide, gadolinium oxide, or yttrium oxide, is used to retard or block dopants from diffusing into the channel regions
Data Source
AI summary
A semiconductor structure includes a substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers are over the substrate and spaced apart from each other in a Z-direction. The source/drain features are over the substrate. The semiconductor layers are between the source/drain features. The metal oxide layers are on top surfaces and bottom surfaces of the semiconductor layers. The gate structure covers and is in contact with center portions of the metal oxide layers on top surfaces and bottom surfaces of the semiconductor layers.