Semiconductor Package Metal Pillars Prevent Solder Bridging
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Solution Overview
Problem
Conventional semiconductor package structures face issues with solder bridging due to close gaps between contact pads and circuit boards, leading to unreliable solder joints and difficulty in achieving high-density I/O connections.
Innovation Solution
A semiconductor package structure featuring a dielectric layer with metal pillars protruding from its surface, allowing for array-arranged contact pads and shortened bonding wires, which prevent solder bridging and tangling, and facilitate stable solder joints and high-density I/O connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If contact pads are closely arranged to reduce package size, then package size is reduced, but solder bridging occurs due to insufficient gap between contact pads and circuit board
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional structure by making contact pads protrude from the bottom surface of the package. This vertical dimensionality change allows the contact pads to extend downward, creating sufficient gap between the package body and circuit board while maintaining close horizontal arrangement, thereby preventing solder bridging while enabling high-density I/O connections
2Reliability
If contact pads protrude from the package bottom to prevent solder bridging, then solder joint reliability is improved, but package structure complexity increases
Solution Approach 1:
The patent merges the contact pad structure with the lead frame by forming contact pads from the lead frame material itself. The lead frame is configured to have contact pads that naturally protrude from the package bottom, eliminating the need for separate protrusion structures and reducing overall package complexity while achieving the desired gap for reliable soldering
3Productivity
If bonding wires are lengthened to reach array-arranged contact pads, then high-density I/O connections are enabled, but electrical performance deteriorates due to wire tangling and increased inductance
Solution Approach 1:
The patent positions bond pads in three-dimensional space around the semiconductor chip, utilizing vertical and radial arrangements. This spatial distribution allows bonding wires to connect to contact pads without excessive length or tangling, maintaining electrical performance while enabling high-density I/O connections through array arrangement
Data Source
AI summary
A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.