Semiconductor Device Metal Post Sealing Warp Reduction
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Solution Overview
Problem
Stacked-package SiP devices face challenges in simultaneously achieving a lower assembly height and reduced warp, as existing techniques either reduce package thickness at the expense of increased warp or suppress warp at the cost of higher assembly height.
Innovation Solution
A semiconductor device with metal posts on a circuit board, covered by a sealing layer that includes reinforcement material, where only the metal posts are exposed, allowing for a thinner substrate and reduced warp by increasing the rigidity of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the substrate is thinned to reduce assembly height, then the profile is lowered, but package warp increases
Solution Approach 1:
The patent segments the sealing function by providing multiple sealing layers (first sealing layer and second sealing layer) at different locations. The first sealing layer seals the semiconductor element mounting site, while the second sealing layer seals the periphery of the substrate, creating distributed structural support that reduces warp while maintaining thin profile
Solution Approach 2:
The patent uses a composite structure combining the substrate, semiconductor element, multiple sealing layers, and reinforcement members to create a balanced assembly. The reinforcement members (such as ribs or protrusions) integrated into the sealing layers provide additional structural rigidity without significantly increasing overall thickness
2Length of stationary object
If partial molding is used to reduce assembly height, then the profile is lowered, but package warp increases at unmolded regions
Solution Approach 1:
The patent divides the sealing function into two segments: first sealing layers that seal the semiconductor element mounting sites (similar to partial molding), and second sealing layers that specifically seal the periphery and ends of the substrate. This segmentation ensures that previously unmolded peripheral regions now receive sealing and structural support, eliminating warp at the ends while maintaining the low-profile advantage of partial molding
3Stability of the object's composition
If entire surface molding is used to suppress warp, then package stability improves, but assembly height increases
Solution Approach 1:
Instead of using a single thick sealing layer across the entire surface, the patent segments the sealing into two functional layers: first sealing layers localized at semiconductor element sites, and second sealing layers at the periphery. This segmentation provides comprehensive warp suppression through distributed structural support while minimizing the overall thickness and assembly height compared to full-surface molding
Data Source
AI summary
A semiconductor device, in which a semiconductor element is mounted on one side of a circuit board that is made up from an insulating layer and a wiring layer, includes metal posts provided on the side of the circuit board on which the semiconductor element is mounted; and a sealing layer provided on the side of the circuit board on which the semiconductor element is mounted such that the semiconductor element is covered and such that only portions of the metal posts are exposed.