Semiconductor Device With Metal-Semiconductor Compound Layer
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Solution Overview
Problem
Current semiconductor devices face limitations in increasing data storage capacity and improving electrical characteristics, particularly in the design of memory cells and gate electrodes, which affect the overall performance and efficiency of data storage systems.
Innovation Solution
The semiconductor device incorporates a pattern structure with sequentially stacked layers, including a first, second, and third pattern layer, with a metal-semiconductor compound layer contacting the channel layer and extending through the pattern layers, and gate electrodes spaced apart to enhance electrical performance and storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking multiple pattern layers (first, second, and third pattern layers) vertically. This dimensional change enables increased storage capacity within the same footprint area, allowing memory cells to be organized in multiple levels rather than a single plane.
Solution Approach 2:
The memory device is segmented into multiple functional components including separate pattern layers, gate electrodes, and channel structures. Each layer serves specific functions: pattern layers provide structural organization, gate electrodes control charge flow, and channel structures enable electron transport. This segmentation allows independent optimization of each component while maintaining overall system functionality.
2Quantity of substance
If gate electrodes are stacked vertically to increase storage capacity, then storage capacity is improved, but wiring resistance increases
Solution Approach 1:
The patent introduces a metal-semiconductor compound layer as an intermediary between the channel structure and the second pattern layer. This compound layer serves as a mediator that reduces contact resistance and improves electrical connection quality, thereby mitigating the wiring resistance issue that arises from vertical stacking of gate electrodes.
Solution Approach 2:
The patent employs composite material structures including the metal-semiconductor compound layer formed by combining metal and semiconductor materials. This composite approach creates materials with optimized electrical properties that balance conductivity and structural integrity, reducing wiring resistance in the vertically stacked gate electrode configuration.
3Quantity of substance
If pattern layers are stacked sequentially to increase storage capacity, then storage capacity is improved, but noise in common source line increases
Solution Approach 1:
The patent applies local quality optimization by assigning different materials and properties to different regions of the device. The metal-semiconductor compound layer is specifically positioned at critical interfaces where noise reduction is most needed, while other regions maintain their original structures. This localized optimization reduces noise in the common source line without compromising overall storage capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves electrical characteristics by reducing wiring resistance and noise in the common source line, while also optimizing the Schottky barrier control for efficient data storage and retrieval operations.
Implementation Method 1
The metal-semiconductor compound layer may contact the first metal layer of the second pattern layer. At least a portion of the metal-semiconductor compound layer may overlap the lower gate electrode in a second direction.
Data Source
AI summary
A semiconductor device includes a lower structure; a pattern structure including first to third pattern layers sequentially stacked on the lower structure; gate electrodes stacked on the pattern structure and spaced apart from each other in a first direction that is perpendicular to an upper surface of the pattern structure, and a channel structure passing through the gate electrodes. The channel structure includes a channel layer and a metal-semiconductor compound layer. The metal-semiconductor compound layer contacts the channel layer and the second pattern layer. The channel structure passes through the second and third pattern layers and extends into the first pattern layer. The second pattern layer has a first metal layer contacting the metal-semiconductor compound layer. At least a portion of the metal-semiconductor compound layer overlaps the lower gate electrode in a second direction perpendicular to the first direction.