Semiconductor Structure Metal Silicide Formation
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Solution Overview
Problem
In the manufacturing of semiconductor structures, it is challenging to sufficiently secure the area for forming metal silicide, especially in miniaturized openings and those with varying aspect ratios, which affects contact resistance and leakage current.
Innovation Solution
A method involving the formation of silicon regions and metal-silicon regions in openings with different aspect ratios, including the use of sidewall spacers in some openings, to concurrently form metal silicide in both memory cell and peripheral circuit regions, ensuring adequate area for metal silicide formation and improving contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If openings are miniaturized to increase device density, then device integration is improved, but the area for forming metal silicide is insufficient leading to increased contact resistance
Solution Approach 1:
The patent introduces a vertical silicon region extending into the opening, transforming the metal silicide formation from a purely planar interface to a three-dimensional structure. This vertical dimension provides additional surface area for metal silicide formation without increasing the lateral footprint, thereby maintaining low contact resistance while accommodating miniaturized openings.
Solution Approach 2:
The patent embeds a silicon region within the opening structure, creating a nested configuration where the silicon region is contained within the opening and provides a substrate for metal silicide formation. This nested structure allows metal silicide to form on the silicon region's surface and sides, maximizing the contact area within the constrained opening space.
2Manufacturing precision
If sidewall spacers are formed in openings to control metal silicide formation, then manufacturing precision is improved, but the area available for metal silicide formation is reduced
Solution Approach 1:
The patent segments the opening space by introducing a silicon region that divides the opening into distinct zones. The silicon region acts as a separate structural element within the opening, allowing metal silicide to form on its surface and sides, thereby creating multiple formation zones rather than a single constrained space.
Solution Approach 2:
By adding the vertical silicon region, the patent creates additional surface area in the vertical dimension that is not occupied by sidewall spacers. The metal silicide can form on the top surface and lateral surfaces of the silicon region, effectively utilizing the vertical space to compensate for the horizontal space blocked by spacers.
3Reliability
If different opening structures are used for memory cell and peripheral circuit regions, then device performance is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent applies the silicon region structure selectively to specific openings based on their required aspect ratios and performance needs. Memory cell regions may receive silicon regions with different dimensions or configurations compared to peripheral circuit regions, allowing local optimization without requiring completely different manufacturing processes for each region.
Solution Approach 2:
The silicon region is formed in advance before metal deposition, creating a prepared substrate that facilitates subsequent metal silicide formation. This preliminary structuring of the opening with silicon regions standardizes the preparation step across different regions, simplifying the overall manufacturing process while still allowing for regional variations in the final device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for effective area securing of metal silicide, enabling concurrent formation in openings of varying aspect ratios, thereby reducing contact resistance and improving the performance of semiconductor structures.
Implementation Method 1
forming the first metal-silicon region by reacting the silicon region and the metal layer; forming the second metal-silicon region by reacting the second doping region and the metal layer
Implementation Method 2
forming the first metal-silicon region by reacting the silicon region and the metal layer; forming the second metal-silicon region by reacting the second doping region and the metal layer
Implementation Method 3
performing a thermal processing to activate the second dopant in the upper portion of the silicon region to form the first interface doping region
Implementation Method 4
performing a thermal processing to activate the fourth dopant in the second interface doping region
Data Source
AI summary
A method for manufacturing a semiconductor structure includes preparing a semiconductor substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the semiconductor substrate in the memory cell region; forming a bit line structure over the semiconductor substrate in the memory cell region; forming a dielectric layer in the peripheral circuit region and the memory cell region; forming a first opening in the dielectric layer in the memory cell region; filling a silicon filler in the first opening; forming a second opening in the dielectric layer in the peripheral circuit region; forming a sidewall spacer over a sidewall of the second opening; recessing the silicon filler to form a silicon plug, wherein the silicon plug fills a lower portion of the first opening; and forming a first metal silicide over a top surface of the silicon plug, and concurrently forming a second metal silicide in a lower portion of the second opening.