Semiconductor Metal Trace Formation Using Spacer Templates
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in forming precise and efficient connections between conductive layers separated by dielectric layers, particularly in achieving consistent and scalable dimensions for metal traces and dielectric widths, which affects the overall semiconductor arrangement's performance and size.
Innovation Solution
A method is developed to form semiconductor arrangements by creating specific spacers, metal oxide layers, and photoresist openings to define patterns that are then transferred to dielectric and metal layers, allowing for the formation of metal traces with controlled widths and lengths, and dielectric openings with precise dimensions, using techniques like atomic layer deposition and chemical mechanical planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional semiconductor manufacturing techniques are used to form connections between conductive layers, then the process is simpler, but the precision and consistency of metal trace widths and dielectric opening dimensions are insufficient
Solution Approach 1:
The patent applies preliminary action by forming spacers and metal oxide layers before defining the final metal trace patterns. The spacers are deposited and patterned first, then used as templates to guide subsequent etching and metal deposition, ensuring precise dimensional control is achieved before final trace formation
Solution Approach 2:
The fabrication process is segmented into multiple discrete steps: spacer formation, metal oxide deposition, photoresist patterning, etching, and metal trace deposition. Each step independently contributes to the final precision, allowing complex outcomes to be achieved through manageable, sequential operations
2Productivity
If traditional manufacturing methods are used, then the process steps are fewer, but the scalability and consistency of dimensions across different arrangement sizes are poor
Solution Approach 1:
The patent utilizes parameter changes by varying the dimensions of spacers and metal oxide layers to define different metal trace widths and dielectric opening sizes. By controlling spacer thickness, metal oxide layer thickness, and photoresist opening dimensions, the process achieves consistent scaling across different device geometries
Solution Approach 2:
Spacers and metal oxide layers serve as intermediary structures that mediate between the photoresist pattern and the final metal trace geometry. These intermediaries ensure that dimensional information is accurately transferred and scaled, enabling consistent fabrication across different device sizes
3Manufacturing precision
If precise dimensions are achieved through multiple fabrication steps, then manufacturing precision improves, but the number of process steps increases
Solution Approach 1:
The patent merges multiple functions into single process steps where possible. For example, the spacer formation process simultaneously defines the width of both the metal trace and the dielectric opening, and the metal oxide deposition serves both as a protective layer and as a dimensional template for subsequent etching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of semiconductor structures with metal traces and dielectric openings of precise dimensions, enhancing connectivity and scalability, leading to improved semiconductor performance and smaller arrangement sizes compared to traditional methods.
Implementation Method 1
using techniques like atomic layer deposition
Implementation Method 2
using techniques like atomic layer deposition and chemical mechanical planarization
Data Source
AI summary
A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a first metal trace having a first metal trace width between about 30 nm to about 60 nm and a first metal trace length. A second metal trace has a second metal trace width between about 10 nm to about 20 nm and a second metal trace length, the first metal trace length different than the second metal trace length. A dielectric layer is between the first metal trace and the second metal trace. The dielectric layer has a dielectric layer width between the first metal trace and the second metal trace between about 10 nm to about 20 nm. The semiconductor arrangement is formed in a manner that allows metal traces having small dimensions to be formed where the metal traces have different dimensions from one another.