Semiconductor Device Metal Wiring Erasing
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Solution Overview
Problem
Current nonvolatile flash memory devices, such as NOR and NAND flash memories, face challenges in achieving high-speed erasing operations and reducing power consumption due to the inefficiencies in charge extraction from floating gates through tunnel insulating films, leading to prolonged erasing times and high power consumption.
Innovation Solution
The semiconductor device incorporates a metal wiring layer with low resistivity materials like Al or Cu, overlapping with a floating gate and an oxide semiconductor layer containing In, Ga, and Zn, which facilitates rapid charge extraction by applying electric fields across the entire surface of the floating gate, reducing the need for high voltage and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge is extracted from the floating gate through the tunnel insulating film to the source or drain, then data is erased, but the erasing operation takes a long time and power consumption is high
Solution Approach 1:
The patent divides the charge extraction path into multiple segments by introducing intermediate conductive layers (first and second conductive layers) between the floating gate and the source/drain. This segmentation allows charge to be extracted through multiple parallel paths simultaneously, significantly reducing erasing time while maintaining data storage reliability.
Solution Approach 2:
The patent introduces intermediate conductive layers and insulating films as mediators in the charge extraction process. These intermediate layers facilitate controlled charge transfer from the floating gate to the source/drain, enabling faster extraction without compromising the integrity of the tunnel insulating film and maintaining reliable data storage.
2Reliability
If high voltage is applied to the gate electrode for erasing operation, then charge is extracted from the floating gate, but power consumption increases
Solution Approach 1:
The patent segments the voltage application structure by introducing multiple conductive layers at different positions. This allows the application of lower voltages across multiple stages rather than requiring a single high voltage, thereby reducing overall power consumption while maintaining effective charge extraction efficiency.
Solution Approach 2:
The intermediate conductive layers and insulating films act as voltage distribution mediators, enabling the gate electrode voltage to be distributed across multiple interfaces. This mediation reduces the peak voltage requirement and associated power consumption while preserving the charge extraction efficiency needed for reliable erasing operations.
3Reliability
If charge passes through the tunnel insulating film at the edge of the floating gate, then erasing is achieved, but the process is inefficient and time-consuming
Solution Approach 1:
The patent introduces multiple conductive layers that create multiple parallel charge extraction paths across the floating gate surface. This segmentation distributes the charge extraction process across numerous simultaneous pathways, dramatically increasing erasing speed while ensuring complete charge removal and maintaining extraction completeness.
Solution Approach 2:
The patent transitions from a single-point or edge-based charge extraction mechanism to a multi-dimensional array of extraction paths through the stacked conductive layers. This dimensional expansion of the extraction architecture enables parallel processing of charge across the entire floating gate surface, significantly boosting productivity without sacrificing completeness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables faster erasing operations and lower power consumption compared to conventional methods, while also improving the reliability of the semiconductor device by reducing dielectric breakdown and increasing the number of rewriting cycles.
Implementation Method 1
facilitates rapid charge extraction by applying electric fields across the entire surface of the floating gate
Implementation Method 2
the charge passes through a region of the tunnel insulating film in the vicinity of an edge of the floating gate
Data Source
AI summary
In a semiconductor device using a nonvolatile memory, high speed erasing operation and low power consumption are realized. In a nonvolatile memory in which a channel formation region, a tunnel insulating film, and a floating gate are stacked in this order, the channel formation region is formed using an oxide semiconductor layer. In addition, a metal wiring for erasing is provided in a lower side of the channel formation region so as to face the floating gate. With the above structure, when erasing operation is performed, charge accumulated in the floating gate is extracted to the metal wiring through the channel formation region. Consequently, high speed erasing operation and low power consumption of the semiconductor device can be realized.