Semiconductor Metallisation Patterning for Low Rds(on) and Edge Robustness
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Solution Overview
Problem
Semiconductor devices face a trade-off between low on-resistance (Rds(on)) and mechanical robustness due to the opposing requirements of a thick metallisation layer for electrical performance and a thin layer for mechanical stability, with dual-layer metallisation techniques being costly and complex.
Innovation Solution
A method involving a single additional photolithography stage and removal process to achieve varying metallisation layer thicknesses, allowing for full thickness in active areas and reduced thickness in edge areas without additional chemical mechanical planarization (CMP) processing, using selective etching and interleaved layers to maintain both low Rds(on) and mechanical robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick metallisation layer is used, then low on-resistance (Rds(on)) is achieved, but mechanical robustness deteriorates due to passivation layer cracking
Solution Approach 1:
The patent applies different metallisation layer thicknesses to different regions of the semiconductor device. The active area receives a thick metallisation layer (first thickness) to minimize Rds(on), while the edge termination area receives a thin metallisation layer (second thickness) to prevent passivation cracking. This spatial differentiation of layer thickness resolves the contradiction between electrical performance and mechanical robustness.
2Reliability
If dual-layer metallisation techniques are used to satisfy both electrical and mechanical requirements, then both low Rds(on) and mechanical robustness are achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent changes the thickness parameter of a single metallisation layer differently across various regions of the device. By controlling the deposition and selective removal processes, the metallisation layer achieves two distinct thicknesses (first thickness in active area, second thickness in edge area) without requiring dual-layer metallisation. This parameter-based approach simplifies the device structure while maintaining both electrical and mechanical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of lithography masks required, minimizes passivation cracks, and enhances mechanical robustness while maintaining low gate resistance, thereby improving the overall performance and reliability of semiconductor devices like power MOSFETs.
Implementation Method 1
a layer of metallic material is deposited onto a substrate
Implementation Method 2
removing metal material from the edge area according to the first mask, whereby a first portion of the edge area has a thickness intermediate the substrate and the layer top surface
Implementation Method 3
removing metal material from the first portion according to the second mask, whereby at least a second portion of the edge area is free of deposited metallic material
Data Source
AI summary
A semiconductor device and method of manufacturing the semiconductor device is disclosed. A layer of metallic material is deposited onto a substrate, the layer having a top surface. At least an edge area of the layer is masked with a first lithography mask and metallic material is removed from the edge area according to the first mask, whereby a first portion of the edge area has a thickness intermediate to the substrate and the layer top surface. The first portion of the edge area is masked with a second lithography mask and metallic material is removed from the first portion according to the second mask, whereby second portions of the edge area are free of deposited metallic material.